• Thanks for your patience. Your understanding is correct. Please wait for few more weeks.

  • Hello there,

    Not to be pushy, but is this no-OS build still going to be released in the next week or two? Our team has been struggling and this would be immensely helpful in getting us up and running. My understanding from your post is that source code will be provided and so fully modifiable? SW and HDL? Thanks.

  • gverma,

    Is this some thing that has progressed since January (providing more complete code for reference platform ZC706)? My understanding is that you have implemented the ZC706 specific functions for common.c and the equivalent of headless.c in your linux image and for the AdiCmdServerClient (cmd_server) used by TES and the ZC706, just not released.  Releasing these files would get your customers up and running much sooner than currently can.  I am fairly new to the the ADI platform (total newbie), but my colleagues that have used no-os and AD9361 in the past were expecting this to be a lot more implemented (since it is a reference platform and you want to get people up and running ASAP).

    I'm not sure what order devs are attacking the required items and what resources to implement or how more experienced developers are figuring out what needs to be done and when. I'm at the point where I'm trying to implement the JESD204B initialization. I have the FPGA_setup* and FPGA_resetFpgaIP code that was pasted into this thread (that is what is used in ADI's linux implementation?) as my reference to implement in no-os initialization.

    The mykonos_api_source_v3546.0 source includes example files myk_fpga_init.c and myk_fpga_init.h (which were not in the previous API source release), but not mykonos_fpga_ip.h and mykonos_fpga_ip.c (not even skeleton functions and structs like common.c reference), which is a good chunk of the work. At this point, I've used the myk_fpga_init example files and the Mykonos_TCPIP_Client_Library.chm document found in the RadioVerse folder to create the skeleton files for mykonos_fpga_ip.  When comparing the generated python script, I can match up the python commands with the pasted FPGA commands provided except for the serializer/deserializer config.  I am suspicious of RadioVerse missing these in the generated python file as a bug, but not sure (initJESD section has 3 commands for framing and none for de/serializer).



    In the Mykonos_TCPIP_Client_Library.chm document, Classes->Class List->FpgaMykonos->* list all the functions implemented in your TES/Linux code.  I'm hoping that using these descriptions and ZC706 userguide, I can implement the required FPGA initialize functions (task for tomorrow).  But there appears to be a lot more FPGA related functions in the Mykonos_TCPIP_Client_Library.chm document, so I'll probably implement them as they are deemed necessary (gets through initialization, and then whatever to support other devs testing their FPGA code).

    So in the absence of complete reference platform no-os source code, having more verbose instructions/details on implementing all the functions other than "Add API code  along with file contains the main function e.g. ‘headless.c’ generated by GUI, device HAL and platform HAL specific into project" and "You will see compilation errors related to platform and fpga specific files, which need to implement as per interface defined in ‘common.h’ on customer platform."


    Unless I really misunderstand and I DON'T need  to do any FPGA initialization in headless.c nor implement myk_fpga_init or mykonos_fpga_ip files, these files are not mentioned in the AD9371 Software Build Instructions.docx. I would also suggest changing your response to the no-os build instructions "Build steps on reference fpga platform to be added" if you're not actually going to.  Otherwise, the customer is under the impression it is coming, and not in 6+ months to never (sounds like it was cancelled and no plans to release).

    I would love to hear from anyone  who has successfully implemented AD9371 with no-os please chime in with a little summary of the integration efforts or what got you past your blocking point that wasn't obvious (or in my case, obvious to anyone else but a newb).

    Much appreciated!


  • Thanks for your patience. We are working on a No-OS build and you can expect a release in coming 3 to 4 weeks of time frame.

    This will be a complete build with open FPGA design, complete HAL layer source code and bare metal tool chain and a dedicated e-zone forum.