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When I load my Matlab generated profile in TES and generate C code initialization scripts, the board pll doesn't lock

Hi, as the title says, I am having problems with making my TX-RX profiles to work with the board and no-os code.

I have a specific requirement for the TX and RX filters so I had to use the Matlab profile generator. My IQ sampling rate is the supported 153.6MHz using the onboard crystal oscillator. Whenever I use the generated myk.c and myk_ad9528init.c files, the ad9371 pll does not lock.

When I generate the myk.c and myk_ad9528init.c from one of the default profiles in TES (TX/RX BW =100MHz, IQrate=153.6MHz) and use it, the board initialize without a problem. Also, I confirmed that it transmits the 1MHz sine wave and also receives it when I loop it back.

Now my thoughts are

1. The Matlab generated profiles worked when I load it and run it in TES . I was able to transmit and receive a signal through a loopback. The problem is when I generate the script and run them in no Os code. So I guess this is a bug in the TES script generation of myk.c and myk_ad9528init.c?

2. Because the non-default profile and default profile have the same IQ rate and TX-RX carrier frequencies, I would assume that they should have the same myk_ad9528init.c contents. Is this correct? While the two files are very similar, they are not the same. So what I did is to use the myk_ad9528init.c from the default profile to replace my non-default profile and indeed the ad9371 pll locked! However, there is no output from the Transmitter. The receiver works fine though.

I attached my profiles for reference.
  • There is a bug in latest GUI v2067 where GUI is not initializing 'CLKPLL VCO divider' correctly to match with custom profile. Only work around is to manually match the structure values with your custom profile. We are working on getting this issue fixed.


    * \brief Data structure to hold digital clock settings


    typedef struct


    uint32_t deviceClock_kHz; /*!< CLKPLL and device reference clock frequency in kHz */

    uint32_t clkPllVcoFreq_kHz; /*!< CLKPLL VCO frequency in kHz */

    mykonosVcoDiv_t clkPllVcoDiv; /*!< CLKPLL VCO divider */

    uint8_t clkPllHsDiv; /*!< CLKPLL high speed clock divider */

    } mykonosDigClocks_t;

    This will be in generated .c file like below

    static mykonosDigClocks_t mykonosClocks =
        80000,          /* CLKPLL and device reference clock frequency in kHz*/
        9600000,        /* CLKPLL VCO frequency in kHz*/
        VCODIV_1,       /* CLKPLL VCO divider*/
        4               /* CLKPLL high speed clock divider*/

  • Hi,

    So how can I compute the actual values of these settings?

  • You need to change CLKPLL VCO divider in mykonosDigClocks_t instance to match clkPllVcoDiv value used in custom profile.  

    if your custom profile has <clkPllVcoDiv=2>, then the script should have vco divider as VCODIV_2

  • Thanks, it is already working now. I will test if the filters really work correctly as set.