Hello
I have an ADRV9375 evaluation board that I am using with a ZCU102. I have used the ADI 2022_R2 HDL reference design to build the FPGA firmware in Vivado. I am using the ADI 2022_R2 meta ADI layer in Petalinux. It is working in the following configuration:
RX: 125MSPS, 2 channels, 2 JESD lanes
ORX: 250MSPS, 1 channel, 2 JESD lanes
TX: 250MSPS, 2 channels, 4 JESD lanes
The customer has now requested that I change the configuration and allocate all four RX JESD lanes to the RX channel. So the configuration becomes:
RX: 166.67MSPS, 2 channels, 4 JESD lanes
ORX: 166.67MSPS, only internal to the AD9375, no data to the FPGA
TX: 166.67MSPS, 2 channels, 4 JESD lanes
I am about to start making the changes to the FPGA HDL firmware so that all four RX JESD lanes are allocated to the RX.
However, I wanted to check:
1) Is this configuration (all 4 lanes allocated to RX with no OBS RX) supported by the IIO Linux device driver?
2) If so, what are the required updates to the device tree to support this configuration? I assume I need to make changes to the JESD framer configuration in the device tree.
3) If not, how extensive would the changes need to be to the IIO Linux device driver to support this mode? Some guidance would be greatly appreciated.
Thank you.