A spurious signal suspected of being a harmonic of 122.88MHz, which is the JESD reference clock of AD9375, is observed on the custom board we made. Unfortunately, this spur exists within the service band. So we're going to start with the most suspicious JESD link. In the FPGA connected to the AD9375, the JESD output current can be adjusted.
Please answer whether the AD9375 has such a function. It doesn't seem to exist in the API.