AD9375 TX Only Mode creation

Are you using custom board or eval board? If you run without disabling the RX path, are you able to run the full initialization?

Can you use the below API to and check that which cal is failing in RX only mode? 

MYKONOS_getInitCalStatus

Yes we are using a custom board and we are able to run full initialization without disabling the RX path. we are able to use the RX, TX and ORX without any issue.

we used the API 'MYKONOS_getInitCalStatus' to find the error. The error occurred because we are trying to configure RXLO frequency after turning off the RX.

Now we removed all the RX related initialization and configurations from the 'Headless_main()' and it is getting initialized successfully.

After initializing with RX path Off (TX and ORX enabled), we are not receiving the k character from the GTH core of ORX JESD line but the TX is working as per the requirement.

we are using only First JESD lane for ORX and next two lanes for RX in both Rx On and RX Off conditions

we are using the below mentioned Profile configuration (TX and ORX On, RX Off)

Framer configuration

static mykonosJesd204bFramerConfig_t rxFramer =

{

    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/

    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/

    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/

    4,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/

    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/

    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/

    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/

    0x06,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/

    0x08,           /* serializerLaneCrossbar*/

    22,             /* serializerAmplitude - default 22 (valid (0-31)*/

    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/

    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/

    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/

    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/

    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/

    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/

    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/

    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/

    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/

};

static mykonosJesd204bFramerConfig_t obsRxFramer =

{

    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/

    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/

    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/

    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/

    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/

    0,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/

    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/

    0x01,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/

    0x00,           /* Lane crossbar to map framer lane outputs to physical lanes*/

    22,             /* serializerAmplitude - default 22 (valid (0-31)*/

    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/

    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/

    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/

    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/

    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/

    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/

    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/

    1,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/

    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/

};

RX Settings

static mykonosRxSettings_t  rxSettings =

{

    &rxProfile,     /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/

    &rxFramer,      /* Rx JESD204b framer configuration structure*/

    &rxGainControl, /* Rx Gain control settings structure*/

    &rxAgcConfig,   /* Rx AGC control settings structure*/

    0,              /* The desired Rx Channels to enable during initialization*/

    0,              /* Internal LO = 0, external LO*2 = 1*/

    1330000000U,    /* Rx PLL LO Frequency (internal or external LO)*/

    0               /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/

};

ORX Settings

static mykonosObsRxSettings_t obsRxSettings =

{

    &orxProfile,    /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/

    &orxGainControl,/* ObsRx gain control settings structure*/

    &obsRxAgcConfig,/* ORx AGC control settings structure*/

    &snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/

    &snifferGainControl,/* SnRx gain control settings structure*/

    &obsRxFramer,   /* ObsRx JESD204b framer configuration structure */

    (MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */

    OBSLO_TX_PLL,   /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */

    1350000000U,    /* SnRx PLL LO frequency in Hz */

    0,              /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/

    NULL,           /* Custom Loopback ADC profile to set the bandwidth of the ADC response */

    OBS_RXOFF       /* Default ObsRx channel to enter when radioOn called */

};

kindly share us the solution.

Thanks,
Deva

Deva1998 said:

we are using only First JESD lane for ORX and next two lanes for RX in both Rx On and RX Off conditions

How are you assigning lanes to RX, when RX is disabled in initialization? Also, are you assigning one lane to ORX? Note that you need to assign two lanes for ORX framer  and the other two lanes for RX framer for both RX and ORX enabled case.

Can you check the signal integrity of the links connecting framer to deframer?Use PRBS fro verifying the link.

Deva1998 said:

we are using only First JESD lane for ORX and next two lanes for RX in both Rx On and RX Off conditions

How are you assigning lanes to RX, when RX is disabled in initialization? Also, are you assigning one lane to ORX? Note that you need to assign two lanes for ORX framer  and the other two lanes for RX framer for both RX and ORX enabled case.

Can you check the signal integrity of the links connecting framer to deframer?Use PRBS fro verifying the link.

Hi!

let me explain in brief,

Case1: Working(ENABLED -> RX1,RX2,ORX1,ORX2,TX1,TX2,SnifferA,B,C)
JESD Lane configuration are as follows,
RX
mykonosRxSettings_t->rxChannels =  3
mykonosJesd204bFramerConfig_t->M = 4
mykonosJesd204bFramerConfig_t->serializerLanesEnabled = 0x6(lanes 1,2)

ORX
mykonosObsRxSettings_t->obsRxChannelsEnable = MYK_ORX1_ORX2 | MYK_SNRXA_B_C,
mykonosJesd204bFramerConfig_t->M = 2,
mykonosJesd204bFramerConfig_t->serializerLanesEnabled = 0x1(lane 0)

In this case we are able configure initCalMask and are receiving ORX data from JESD without any bit errors.

Case2: Not working(ORX1,ORX2,TX1,TX2,SnifferA,B,C)

JESD Lane configuration are as follows,
RX
mykonosRxSettings_t->rxChannels =  0
mykonosJesd204bFramerConfig_t->M = 4
mykonosJesd204bFramerConfig_t->serializerLanesEnabled = 0x6(lanes 1,2)

ORX
mykonosObsRxSettings_t->obsRxChannelsEnable = MYK_ORX1_ORX2 | MYK_SNRXA_B_C,
mykonosJesd204bFramerConfig_t->M = 2,
mykonosJesd204bFramerConfig_t->serializerLanesEnabled = 0x1(lane 0)

In this case, we are able to configure initCalMask successfully but we are not receiving ILAS characters in the JESD lane of ORX when Sync is low.
The only change we have done is turned off RX and Disabled all the RX related configurations(RX Pll, Gain, Framer) in the headless_main.c.


As per your suggestion, we set the  mykonosJesd204bFramerConfig_t->M = 0, and still the same is observed.

Our requirement is to Configure AD9375 with One TX and One ORX and its JESD.
At present we have configured with Turning RXOFF but are getting stuck in JESD ILAS.
Please share any Example code/profile that would help us in resolving the issue.

Thanks in-advance

Deva

Deva1998 said:

mykonosJesd204bFramerConfig_t->serializerLanesEnabled = 0x6(lanes 1,2)

Can you change the lane selection for RX to zero, i.e, keep the L value to 0.

Similarly, select two lanes for ORX and keep the selected lanes for ORX to lane 2, lane3.

Can you try initializing the board with the above changes and then check if you are seeing the issue?