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AD9375 DAC Output spur

Category: Software

I am using AD9375 interfaced with Xilinx Mpsoc +XCZU11EG. 

In DAC output, (DDS and NCO)I getting spurs around my Output frequency ( where delta is around 25kHz and 50kHz) which is degrading my SFDR . RBW - 100Hz, 

My sampling rate is 245.76MSPS and device  clock is 122.88MHz and single shot  SYSREF -> 0.96MHz

I have checked my clock output, i got exact frequency what i need which is attached below without spurs.

Then i checked all my Regulators OUTPUT.  In 25KHz , i am getting around -80dBm. (too Less)

 Kindly let me know why this is 25kHz ( Delta Tone) is there near to the output frequency

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  • That 25kHz is close to my LO+MSG not to my LO. If i change my LO 

    Like LO = 4500MHz and Message = 10MHz . I can observe the spur at (4510Mhz -25kHz) and (4510+25kHz). 

    LO=4600MHz and Message = 10MHz. I can observe the spur at (4610-25kHz) and (4610-25kHz)

    I don't have any choice to provide external LO.

    Even i have checked ADRV9371 EVM, from 0to 100kHz, Noise floor is around -80dBm.

    Few rails have maximum peak.

    Same, Noise floor we are acheiving in Custom Board. But we have peaks at 25kHz and 50kHz(Less than -80dBm). Thats the only limit

    Could you let me know the API function for configuring LOOP filters of Synthesizers of RX, TX and ORX

  • Even if i reduce the tone, spurs are reducing but little (around 1dB). not more than that.

    How much power was reduced in dBFS?. Can you reduce by -6dBFS and check.

    You can use the API setRfPllLoopFilter(),  to set the PLL loop bandwidth.