Category: Software
Software Version: 2019R2
Hello,
I am using ADRV9375 with ZC706 and using 2019R2 version of HDL and No-OS application.
I want to change My Tx IQ rate to 122.88MSPS, in No-OS application default it is set to 245.76MSPS when I configured Tx IQ rate to 122.88MSPS JESD lane is getting stuck at ILAS state, error log is added below
log_tx_245p76msps_iq_rate log file contains log with TX IQ rate set to 245.76MSPS(default) -- Log is proper and JESD is in DATA state.
log_tx_122p88msps_iq_rate log file contains log with TX IQ rate set to 245.76MSPS-- JESD is in ILAS state.
TX profile for 245.76MSPS IQ rate :
static mykonosTxProfile_t txProfile =
{
/* Tx 75/200MHz, IQrate 245.76MSPS, Dec5 */
DACDIV_2p5, /* The divider used to generate the DAC clock*/
&txFir, /* Pointer to Tx FIR filter structure*/
1, /* The Tx digital FIR filter interpolation (1,2,4)*/
2, /* Tx Halfband1 filter interpolation (1,2)*/
1, /* Tx Halfband2 filter interpolation (1,2)*/
1, /* TxInputHbInterpolation (1,2)*/
245760, /* Tx IQ data rate in kHz*/
75000000, /* Primary Signal BW*/
200000000, /* The Tx RF passband bandwidth for the profile*/
189477, /* The DAC filter 3dB corner in kHz*/
100000, /* Tx BBF 3dB corner in kHz*/
0 /* Enable DPD, only valid for AD9373*/
};TX profile for 122.88MSPS IQ rate :
//Tx IQrate 122.88MSPS
static mykonosTxProfile_t txProfile =
{
/* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */
DACDIV_2p5, /* The divider used to generate the DAC clock*/
&txFir, /* Pointer to Tx FIR filter structure*/
2, /* The Tx digital FIR filter interpolation (1,2,4)*/
2, /* Tx Halfband1 filter interpolation (1,2)*/
1, /* Tx Halfband2 filter interpolation (1,2)*/
1, /* TxInputHbInterpolation (1,2)*/
122880, /* Tx IQ data rate in kHz*/
20000000, /* Primary Signal BW*/
100000000, /* The Tx RF passband bandwidth for the profile*/
710539, /* The DAC filter 3dB corner in kHz*/
50000, /* Tx BBF 3dB corner in kHz*/
0 /* Enable DPD, only valid for AD9373*/
};Please suggest me how to proceed further.
Regards,
Jaydeep
