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AD9375 Rx to Tx loopback issue

Category: Software
Software Version: 2019R2


In my custom board I am interfacing AD9375 with Zynq Ultrascale plus MPSoC (XCZU11EG-ffvc1156).
I am using version of HDL code and No-OS application.

I am doing Rx to Tx loopback in RTL through BRAM,BRAM is used to synchronize the ADC data with DAC clock.

DAC sampling rate : 245.76MSPS

ADC sampling rate : 122.88MSPS

ADC to DAC data path :


A 4503 MHz single tone signal generated from VSG is fed to ADC, same thing shall be observed at DAC output in VSA as I have done loopback Rx to Tx loopback inside RTL.

ADC and DAC LO frequency : 4500MHz

Observed DAC output in VSA, it has image components at LO-MSG and Lo+/-ADC sampling rate. I have captured DAC output and added here, can you please look into this and let us know what could be the issue.



  • can you check the I Q mapping in the loopback logic?

    Can you check the loopback if its working correctly or not internal to the chip using the below spi writes? Note that the below loopback is purely for test purpose and should not be used for any application.

    temp = Link.spiRead(0x100)
    Link.spiWrite(0x100, temp |0xC0)