Hello,
In my custom board I am interfacing AD9375 with Zynq Ultrascale plus MPSoC (XCZU11EG-ffvc1156).
I am using version of HDL code and No-OS application.
I am doing Rx to Tx loopback in RTL through BRAM,BRAM is used to synchronize the ADC data with DAC clock.
DAC sampling rate : 245.76MSPS
ADC sampling rate : 122.88MSPS
ADC to DAC data path :
VSG-->AD9375-->RX_AD_XCVR-->AXI_AD9371_RX_JESD-->RX_AD9371_TPL_CORE-->FIR_DECIMATOR-->BRAM
VSA-->AD9375-->TX_AD_XCVR-->AXI_AD9371_TX_JESD-->TX_AD9371_TPL_CORE-->FIR_INTERPOLATOR<--BRAM
A 4503 MHz single tone signal generated from VSG is fed to ADC, same thing shall be observed at DAC output in VSA as I have done loopback Rx to Tx loopback inside RTL.
ADC and DAC LO frequency : 4500MHz
Observed DAC output in VSA, it has image components at LO-MSG and Lo+/-ADC sampling rate. I have captured DAC output and added here, can you please look into this and let us know what could be the issue.
Regards,
Naveen
