Hi,
I am trying to use ZC706 and AD9375 with TES.
I am using a 30.72 MHz external clock for the AD9375
I am getting the following message "AD9528 clock not synchronized"
How can I solve this?
Thanks,
Yaniv
AD9528
Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
Datasheet
AD9528 on Analog.com
AD9371
Recommended for New Designs
The AD9371 is a highly integrated, wideband RF transceiver
offering dual channel transmitters and receivers, integrated synthesizers, and digital signal...
Datasheet
AD9371 on Analog.com
AD9258
Production
The AD9258 is a dual, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9258 is designed to support communications applications...
Datasheet
AD9258 on Analog.com
AD9375
Recommended for New Designs
The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers...
Datasheet
AD9375 on Analog.com
Hi,
I am trying to use ZC706 and AD9375 with TES.
I am using a 30.72 MHz external clock for the AD9375
I am getting the following message "AD9528 clock not synchronized"
How can I solve this?
Thanks,
Yaniv
Did you check the clock setting tab in the TES GUI? Is the REF_CLK set to 30.72MHz there?
I have the same issue, I checked the Ref Clock of AD9528 and it is 30.72MHz. Please let me know if other configuration are needed to be checked.
Thanks
Did you check the REF_Clk parameter in GUI? Is it set to 30.72MHz?
I did check that one as well and it was right.
I realize while TES is running, I cannot reset FPGA. If FPGA has been reset, I need to also reset TES otherwise I will get this error.
Thanks
Are you still having the issue?
If you are restarting the board without disconnecting the TES GUI from the board this issue can happen.
No issue anymore. Thanks for your help.
No issue anymore. Thanks for your help.