No output from AD9082 DAC

Hi, could you confirm that JESD link status on DAC path is also on "Data"?

-YH

Hey, thanks for replying!

Yes, both rx and tx are on DATA, sorry for not mentioning it in the post:

Obviously, I noticed the alignment error which I don't recall being there before, but solving that might be the solution overall. I stumbled upon this thread:

 Versal AD9082 FMCA-EBZ M4 L8 JESD204C design - cont. (SYSREF alignment error) 

Which described the same issue on a VPK120 board, which I also own and tried to use with AD9082 to no success. I went back to the VCK180 because of that but using the VPK120 is actually more beneficial for me.

I'm pretty lost with that issue so let me know if there is any more info I can provide that will help

Thank you!

Thank you for sharing details. Could you take a look at this page : https://analogdevicesinc.github.io/hdl/library/jesd204/troubleshoot/troubleshoot_jesd204_tx.html

Hey, thank you for information. I think my design had some timing violations caused by Xilinx Logic Analyzers. I was to able to fix the issue and now jesd_status is proper:

But I still see no output from the DAC, same as before. In the ILAs the Link interface looks fine and JESD signals also look fine so I'm not sure how to tackle this issue next. I would gladly take any advice, thank you!

I will attach some more relevant info:
my device tree:

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/jesd204/adxcvr.h>

/include/ "system-conf.dtsi"

/* RX path */
#define AD9081_RX_LANERATE_KHZ	24750000
#define AD9081_RX_LINK_CLK	375000000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	24750000
#define AD9081_TX_LINK_CLK	375000000

/ {
	model = "Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A";

	chosen {
		bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
		stdout-path = "serial0:115200";
	};

	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;

		clocks {
			rx_fixed_linerate: clock@0 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LANERATE_KHZ>;
				clock-output-names = "rx_lane_clk";
			};

			tx_fixed_linerate: clock@1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LANERATE_KHZ>;
				clock-output-names = "tx_lane_clk";
			};

			rx_fixed_link_clk: clock@2 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LINK_CLK>;
				clock-output-names = "rx_link_clk";
			};

			tx_fixed_link_clk: clock@3 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LINK_CLK>;
				clock-output-names = "tx_link_clk";
			};
		};

		axi_gpio: gpio@a4000000 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&versal_clk PMC_PL0_REF>;
			compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			interrupt-controller;
			interrupt-names = "ip2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 84 4>;
			reg = <0xa4000000 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x0>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x00000000>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x20>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};

		rx_dma: dma@bc420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc420000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		tx_dma: dma@bc430000  {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc430000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		axi_ad9081_core_rx: axi-ad9081-rx-hpc@a4a10000 {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0xa4a10000 0x8000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
		};

		axi_ad9081_core_tx: axi-ad9081-tx-hpc@a4b10000 {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0xa4b10000 0x4000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
		};

		axi_ad9081_rx_jesd: axi-jesd204-rx@a4a90000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0xa4a90000 0x1000>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 10>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;

			reset-done-gpios = <&axi_gpio 32 0>;
			pll-datapath-reset-gpios = <&axi_gpio 36 0>;
			datapath-reset-gpios = <&axi_gpio 38 0>;
		};

		axi_ad9081_tx_jesd: axi-jesd204-tx@a4b90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0xa4b90000 0x1000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 6>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;

			reset-done-gpios = <&axi_gpio 33 0>;
			pll-datapath-reset-gpios = <&axi_gpio 37 0>;
			datapath-reset-gpios = <&axi_gpio 39 0>;
		};

		axi_sysid_0: axi-sysid-0@a5000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0xa5000000 0x10000>;
		};
	};
};

&gic {
	num_cpus = <2>;
	num_interrupts = <96>;
};

&lpd_dma_chan0 {
	status = "okay";
};

&lpd_dma_chan1 {
	status = "okay";
};

&lpd_dma_chan2 {
	status = "okay";
};

&lpd_dma_chan3 {
	status = "okay";
};

&lpd_dma_chan4 {
	status = "okay";
};

&lpd_dma_chan5 {
	status = "okay";
};

&lpd_dma_chan6 {
	status = "okay";
};

&lpd_dma_chan7 {
	status = "okay";
};

&cci {
	status = "okay";
};

&smmu {
	status = "okay";
};

&i2c1 {
	status = "disabled";
};

&gpio1 {
	status = "okay";
};

&qspi {
	is-dual = <1>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};

&sdhci1 {
	clock-frequency = <199999985>;
	status = "okay";
};

&serial0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
};

&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&ttc0 {
	status = "okay";
};

&ref_clk {
	clock-frequency = <33333333>;
};

&gem0 {
	local-mac-address = [00 0a 35 ad 90 81];
};

&fpga_axi {
	axi_data_offload_tx: axi-data-offload-0@bc440000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc440000 0x10000>;
	};

	axi_data_offload_rx: axi-data-offload-1@bc450000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc450000 0x10000>;
	};
};

&axi_ad9081_core_tx {
	adi,axi-data-offload-connected = <&axi_data_offload_tx>;
	adi,axi-pl-fifo-enable;
};

#define fmc_spi spi0

&spi1 {
	status = "okay";

	hmc7044: hmc7044@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <0>;
		spi-max-frequency = <1000000>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-sysref-provider;

		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

		/*
		 * There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
		 * VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		 * VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		 * To determine which board is which, read the freqency printed on the VCXO
		 * or use the fru-dump utility:
		 * #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
		 */

		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
		//adi,vcxo-frequency = <122880000>;

		adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
		adi,pll1-ref-autorevert-enable;
		adi,vcxo-frequency = <100000000>;

		adi,pll1-loop-bandwidth-hz = <200>;
		adi,pll1-charge-pump-current-ua = <720>;
		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

		adi,pll2-output-frequency = <3000000000>;

		adi,sysref-timer-divider = <1024>;
		adi,pulse-generator-mode = <0>;

		adi,clkin0-buffer-mode  = <0x07>;
		adi,clkin1-buffer-mode  = <0x07>;
		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
		adi,gpo-controls = <0x37 0x33 0x00 0x00>;

		clock-output-names =
		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
		"hmc7044_out12", "hmc7044_out13";

		hmc7044_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS

		};

		hmc7044_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};

		hmc7044_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "CORE_CLK_TX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "FPGA_REFCLK1";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c10: channel@10 {
			reg = <10>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "FPGA_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "FPGA_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};
	};
};

&fmc_spi {

	trx0_ad9081: ad9081@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9082";
		reg = <0>;
		spi-max-frequency = <5000000>;

		/* Clocks */
		clocks = <&hmc7044 2>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		reset-gpios = <&axi_gpio 23 0>;
		sysref-req-gpios = <&axi_gpio 11 0>;
		rx2-enable-gpios = <&axi_gpio 25 0>;
		rx1-enable-gpios = <&axi_gpio 24 0>;
		tx2-enable-gpios = <&axi_gpio 27 0>;
		tx1-enable-gpios = <&axi_gpio 26 0>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

		jesd204-inputs =
		<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
		<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,dac-frequency-hz = /bits/ 64 <12000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};

				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
					adi,link-mode = <17>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3b>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,adc-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
					<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
					<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;

					adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
					adi,link-mode = <18>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */
				};
			};
		};

	};
};

###############################################################################
## Copyright (C) 2024-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# Primary clock definitions
create_clock -name refclk         -period  2.667 [get_ports fpga_refclk_in_p]

# device clock
create_clock -name tx_device_clk  -period 2.667  [get_ports clkin6_p]
create_clock -name rx_device_clk  -period 2.667  [get_ports clkin10_p]

# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_device_clk] \
  [get_property PERIOD [get_clocks tx_device_clk]] \
  [get_ports {sysref2_*}]

Thank you for sharing details. We'll look into the details and get back to you if we find anything.

Just to let you know that we have reproduced the issue and are still investing. It is not clear so far where the trouble is.

We found something interesting regarding your use case. If we apply the following slight modification to the settings, the DAC path works as expected, where the change to use 6 GHz DAC clock with 2x2 interpolation instead of 12 GHz with 2x1

// SPDX-License-Identifier: GPL-2.0
/*
 * Analog Devices AD9081-FMC-EBZ
 * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
 * https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl
 *
 * hdl_project: <ad9081_fmca_ebz/vpk180>
 * board_revision: <>
 *
 * Copyright (C) 2019-2023 Analog Devices Inc.
 */

#include "versal-vpk180-revA.dts"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/jesd204/adxcvr.h>
#include <dt-bindings/iio/frequency/hmc7044.h>
							

/* RX path */
#define AD9081_RX_LANERATE_KHZ	24750000
#define AD9081_RX_LINK_CLK	375000000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	24750000
#define AD9081_TX_LINK_CLK	375000000

/ {
	model = "Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A";

	chosen {
		bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
		stdout-path = "serial0:115200";
	};

	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;

		clocks {
			rx_fixed_linerate: clock@0 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LANERATE_KHZ>;
				clock-output-names = "rx_lane_clk";
			};

			tx_fixed_linerate: clock@1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LANERATE_KHZ>;
				clock-output-names = "tx_lane_clk";
			};

			rx_fixed_link_clk: clock@2 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LINK_CLK>;
				clock-output-names = "rx_link_clk";
			};

			tx_fixed_link_clk: clock@3 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LINK_CLK>;
				clock-output-names = "tx_link_clk";
			};
		};

		axi_gpio: gpio@a4000000 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&versal_clk PMC_PL0_REF>;
			compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			interrupt-controller;
			interrupt-names = "ip2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 84 4>;
			reg = <0xa4000000 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x0>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x00000000>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x20>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};

		rx_dma: dma-controller@bc420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc420000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		tx_dma: dma-controller@bc430000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc430000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		axi_ad9081_core_rx: axi-ad9081-rx-hpc@a4a10000 {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0xa4a10000 0x8000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
		};

		axi_ad9081_core_tx: axi-ad9081-tx-hpc@a4b10000 {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0xa4b10000 0x4000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
		};

		axi_ad9081_rx_jesd: axi-jesd204-rx@a4a90000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0xa4a90000 0x1000>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 10>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;

			reset-done-gpios = <&axi_gpio 32 0>;
			pll-datapath-reset-gpios = <&axi_gpio 36 0>;
			datapath-reset-gpios = <&axi_gpio 38 0>;
		};

		axi_ad9081_tx_jesd: axi-jesd204-tx@a4b90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0xa4b90000 0x1000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 6>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;

			reset-done-gpios = <&axi_gpio 33 0>;
			pll-datapath-reset-gpios = <&axi_gpio 37 0>;
			datapath-reset-gpios = <&axi_gpio 39 0>;
		};

		axi_sysid_0: axi-sysid-0@a5000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0xa5000000 0x10000>;
		};
	};
};

&gic {
	num_cpus = <2>;
	num_interrupts = <96>;
};

&lpd_dma_chan0 {
	status = "okay";
};

&lpd_dma_chan1 {
	status = "okay";
};

&lpd_dma_chan2 {
	status = "okay";
};

&lpd_dma_chan3 {
	status = "okay";
};

&lpd_dma_chan4 {
	status = "okay";
};

&lpd_dma_chan5 {
	status = "okay";
};

&lpd_dma_chan6 {
	status = "okay";
};

&lpd_dma_chan7 {
	status = "okay";
};

&cci {
	status = "okay";
};

&smmu {
	status = "okay";
};

&i2c1 {
	status = "disabled";
};

&gpio1 {
	status = "okay";
};

&qspi {
	is-dual = <1>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};

&sdhci1 {
	clock-frequency = <199999985>;
	status = "okay";
};

&serial0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
};

&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&ttc0 {
	status = "okay";
};

&ref {
	clock-frequency = <33333333>;
};

&gem0 {
	local-mac-address = [00 0a 35 ad 90 81];
};

&fpga_axi {
	axi_data_offload_tx: axi-data-offload-0@bc440000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc440000 0x10000>;
	};

	axi_data_offload_rx: axi-data-offload-1@bc450000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc450000 0x10000>;
	};
};

&axi_ad9081_core_tx {
	adi,axi-data-offload-connected = <&axi_data_offload_tx>;
	adi,axi-pl-fifo-enable;
};

#define fmc_spi spi0

&spi1 {
	status = "okay";

	hmc7044: hmc7044@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <0>;
		spi-max-frequency = <1000000>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-sysref-provider;

		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

		/*
		 * There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
		 * VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		 * VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		 * To determine which board is which, read the freqency printed on the VCXO
		 * or use the fru-dump utility:
		 * #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
		 */

		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
		//adi,vcxo-frequency = <122880000>;

		adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
		adi,pll1-ref-autorevert-enable;
		adi,vcxo-frequency = <100000000>;

		adi,pll1-loop-bandwidth-hz = <200>;
		adi,pll1-charge-pump-current-ua = <720>;
		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

		adi,pll2-output-frequency = <3000000000>;

		adi,sysref-timer-divider = <1024>;
		adi,pulse-generator-mode = <0>;

		adi,clkin0-buffer-mode  = <0x07>;
		adi,clkin1-buffer-mode  = <0x07>;
		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
		adi,gpo-controls = <0x37 0x33 0x00 0x00>;

		clock-output-names =
		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
		"hmc7044_out12", "hmc7044_out13";

		hmc7044_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS

		};

		hmc7044_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};

		hmc7044_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "CORE_CLK_TX";
			adi,divider = <8>;	// 250 = LR/66*4/6
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "FPGA_REFCLK1";
			adi,divider = <8>;	// 750
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c10: channel@10 {
			reg = <10>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 250 = LR/66*4/6
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "FPGA_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "FPGA_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};
	};
};

&fmc_spi {

	trx0_ad9081: ad9081@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9081";
		reg = <0>;
		spi-max-frequency = <5000000>;

		/* Clocks */
		clocks = <&hmc7044 2>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		reset-gpios = <&axi_gpio 23 0>;
		sysref-req-gpios = <&axi_gpio 11 0>;
		rx2-enable-gpios = <&axi_gpio 25 0>;
		rx1-enable-gpios = <&axi_gpio 24 0>;
		tx2-enable-gpios = <&axi_gpio 27 0>;
		tx1-enable-gpios = <&axi_gpio 26 0>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

		jesd204-inputs =
		<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
		<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,dac-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 100 MHz */
				};

				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1100 MHz */
				};

				// ad9081_dac2: dac@2 {
				// 	reg = <2>;
				// 	adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
				// 	adi,nco-frequency-shift-hz = /bits/ 64 <1200000000>;  /* 300 MHz */
				// };

				// ad9081_dac3: dac@3 {
				// 	reg = <3>;
				// 	adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
				// 	adi,nco-frequency-shift-hz = /bits/ 64 <1300000000>; /* 400 MHz */
				// };
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <1>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				// ad9081_tx_fddc_chan2: channel@2 {
				// 	reg = <2>;
				// 	adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				// };

				// ad9081_tx_fddc_chan3: channel@3 {
				// 	reg = <3>;
				// 	adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				// };
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
					adi,link-mode = <17>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,adc-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				// ad9081_adc2: adc@2 {
				// 	reg = <2>;
				// 	adi,decimation = <1>;
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
				// 	adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				// };

				// ad9081_adc3: adc@3 {
				// 	reg = <3>;
				// 	adi,decimation = <1>;
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
				// 	adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				// };
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				// ad9081_rx_fddc_chan4: channel@4 {
				// 	reg = <4>;
				// 	adi,decimation = <1>;
				// 	adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				// };

				// ad9081_rx_fddc_chan5: channel@5 {
				// 	reg = <5>;
				// 	adi,decimation = <1>;
				// 	adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
				// 	adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				// };
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
					<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
					<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;
					// <&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
					// <&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
					adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
					adi,link-mode = <18>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */
				};
			};
		};

	};
};

This confirms that the HDL is not the source of the problem; the issue is most likely related to the software driver that configures the chip. We will continue our investigation. In the meantime, could you please change your DAC clock and interpolation to 6 GHz and 2x1, respectively, to confirm our observations

-YH

Hello! thank you for the suggestions, your help is invaluable. I changed the device tree to the following with your suggested change:

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/jesd204/adxcvr.h>

/include/ "system-conf.dtsi"

/* RX path */
#define AD9081_RX_LANERATE_KHZ	24750000
#define AD9081_RX_LINK_CLK	375000000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	24750000
#define AD9081_TX_LINK_CLK	375000000

/ {
	model = "Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A";

	chosen {
		bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
		stdout-path = "serial0:115200";
	};

	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;

		clocks {
			rx_fixed_linerate: clock@0 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LANERATE_KHZ>;
				clock-output-names = "rx_lane_clk";
			};

			tx_fixed_linerate: clock@1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LANERATE_KHZ>;
				clock-output-names = "tx_lane_clk";
			};

			rx_fixed_link_clk: clock@2 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LINK_CLK>;
				clock-output-names = "rx_link_clk";
			};

			tx_fixed_link_clk: clock@3 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LINK_CLK>;
				clock-output-names = "tx_link_clk";
			};
		};

		axi_gpio: gpio@a4000000 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&versal_clk PMC_PL0_REF>;
			compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			interrupt-controller;
			interrupt-names = "ip2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 84 4>;
			reg = <0xa4000000 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x0>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x00000000>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x20>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};

		rx_dma: dma@bc420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc420000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		tx_dma: dma@bc430000  {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc430000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		axi_ad9081_core_rx: axi-ad9081-rx-hpc@a4a10000 {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0xa4a10000 0x8000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
		};

		axi_ad9081_core_tx: axi-ad9081-tx-hpc@a4b10000 {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0xa4b10000 0x4000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
		};

		axi_ad9081_rx_jesd: axi-jesd204-rx@a4a90000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0xa4a90000 0x1000>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 10>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;

			reset-done-gpios = <&axi_gpio 32 0>;
			pll-datapath-reset-gpios = <&axi_gpio 36 0>;
			datapath-reset-gpios = <&axi_gpio 38 0>;
		};

		axi_ad9081_tx_jesd: axi-jesd204-tx@a4b90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0xa4b90000 0x1000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 6>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;

			reset-done-gpios = <&axi_gpio 33 0>;
			pll-datapath-reset-gpios = <&axi_gpio 37 0>;
			datapath-reset-gpios = <&axi_gpio 39 0>;
		};

		axi_sysid_0: axi-sysid-0@a5000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0xa5000000 0x10000>;
		};
	};
};

&gic {
	num_cpus = <2>;
	num_interrupts = <96>;
};

&lpd_dma_chan0 {
	status = "okay";
};

&lpd_dma_chan1 {
	status = "okay";
};

&lpd_dma_chan2 {
	status = "okay";
};

&lpd_dma_chan3 {
	status = "okay";
};

&lpd_dma_chan4 {
	status = "okay";
};

&lpd_dma_chan5 {
	status = "okay";
};

&lpd_dma_chan6 {
	status = "okay";
};

&lpd_dma_chan7 {
	status = "okay";
};

&cci {
	status = "okay";
};

&smmu {
	status = "okay";
};

&i2c1 {
	status = "disabled";
};

&gpio1 {
	status = "okay";
};

&qspi {
	is-dual = <1>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};

&sdhci1 {
	clock-frequency = <199999985>;
	status = "okay";
};

&serial0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
};

&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&ttc0 {
	status = "okay";
};

&ref_clk {
	clock-frequency = <33333333>;
};

&gem0 {
	local-mac-address = [00 0a 35 ad 90 81];
};

&fpga_axi {
	axi_data_offload_tx: axi-data-offload-0@bc440000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc440000 0x10000>;
	};

	axi_data_offload_rx: axi-data-offload-1@bc450000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc450000 0x10000>;
	};
};

&axi_ad9081_core_tx {
	adi,axi-data-offload-connected = <&axi_data_offload_tx>;
	adi,axi-pl-fifo-enable;
};

#define fmc_spi spi0

&spi1 {
	status = "okay";

	hmc7044: hmc7044@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <0>;
		spi-max-frequency = <1000000>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-sysref-provider;

		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

		/*
		 * There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
		 * VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		 * VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		 * To determine which board is which, read the freqency printed on the VCXO
		 * or use the fru-dump utility:
		 * #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
		 */

		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
		//adi,vcxo-frequency = <122880000>;

		adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
		adi,pll1-ref-autorevert-enable;
		adi,vcxo-frequency = <100000000>;

		adi,pll1-loop-bandwidth-hz = <200>;
		adi,pll1-charge-pump-current-ua = <720>;
		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

		adi,pll2-output-frequency = <3000000000>;

		adi,sysref-timer-divider = <1024>;
		adi,pulse-generator-mode = <0>;

		adi,clkin0-buffer-mode  = <0x07>;
		adi,clkin1-buffer-mode  = <0x07>;
		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
		adi,gpo-controls = <0x37 0x33 0x00 0x00>;

		clock-output-names =
		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
		"hmc7044_out12", "hmc7044_out13";

		hmc7044_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS

		};

		hmc7044_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};

		hmc7044_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "CORE_CLK_TX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "FPGA_REFCLK1";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c10: channel@10 {
			reg = <10>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "FPGA_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "FPGA_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};
	};
};

&fmc_spi {

	trx0_ad9081: ad9081@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9082";
		reg = <0>;
		spi-max-frequency = <5000000>;

		/* Clocks */
		clocks = <&hmc7044 2>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		reset-gpios = <&axi_gpio 23 0>;
		sysref-req-gpios = <&axi_gpio 11 0>;
		rx2-enable-gpios = <&axi_gpio 25 0>;
		rx1-enable-gpios = <&axi_gpio 24 0>;
		tx2-enable-gpios = <&axi_gpio 27 0>;
		tx1-enable-gpios = <&axi_gpio 26 0>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

		jesd204-inputs =
		<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
		<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,dac-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};

				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <1>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
					adi,link-mode = <17>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3b>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,adc-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
					<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
					<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;

					adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
					adi,link-mode = <18>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */
				};
			};
		};

	};
};

I can confirm the new DAC rate through IIO, but I tried to send a CW tone with DDS (/DMA) and unfortunately still got nothing:

It's perhaps a long shot, but I do suspect the TX/RX device clocks are too fast at 375MHz. I wonder if lowering them would maybe help, what are your thoughts? I found a configuration in another post for the vpk180 which shows the following:

Link clock is still 375 MHz but device clocks are at 250MHz. How can I achieve this? I tried changing the clocks in the device tree but I wasn't sure which, there are multiple RX/TX core clocks. I also wonder if changes in the HDL design are needed to change those clocks, I wasn't able to find those configurations in the HDL design blocks.

Let me know if any more info is needed. Thank your for continued support in the matter!

OR1

Sorry to hear of the trouble again. 

The 375MHz link clock is well within the acceptable range, and your configuration does not need a gearbox so the link clock and device clock are same. The other case with 250MHz of device clock that you referenced requires gearbox becuase NP=12, so that is not applicable to you. Refer to the following page for more details about gearbox: analogdevicesinc.github.io/.../fpga_internal.html

So, we'll keep looking. Have you tried any other configuration that works?

-YH

Sorry to hear of the trouble again. 

The 375MHz link clock is well within the acceptable range, and your configuration does not need a gearbox so the link clock and device clock are same. The other case with 250MHz of device clock that you referenced requires gearbox becuase NP=12, so that is not applicable to you. Refer to the following page for more details about gearbox: analogdevicesinc.github.io/.../fpga_internal.html

So, we'll keep looking. Have you tried any other configuration that works?

-YH

It may be worth trying to reduce the clock to see whether it helps. The proposed change is pretty simple as follows

• PLL2 frequency of HMC7044 is reduced from 3GHz to 1.5 GHz, this will scale down all other clocks to 1/2 ratio.
• TX path interpolation radio is changed from 2x2 to 4x2
• RX path decimation ratio is changed from 2x1 to 4x1

As a result, the lane rate and link clock will drop from 24.75GHz and 375 MHz to 12.375 GHz and 187.5 MHz, respectively. I make modifications from your device tree posted before making changes that I suggested.

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/jesd204/adxcvr.h>

/include/ "system-conf.dtsi"

/* RX path */
#define AD9081_RX_LANERATE_KHZ	24750000
#define AD9081_RX_LINK_CLK	375000000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	24750000
#define AD9081_TX_LINK_CLK	375000000

/ {
	model = "Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A";

	chosen {
		bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
		stdout-path = "serial0:115200";
	};

	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;

		clocks {
			rx_fixed_linerate: clock@0 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LANERATE_KHZ>;
				clock-output-names = "rx_lane_clk";
			};

			tx_fixed_linerate: clock@1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LANERATE_KHZ>;
				clock-output-names = "tx_lane_clk";
			};

			rx_fixed_link_clk: clock@2 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LINK_CLK>;
				clock-output-names = "rx_link_clk";
			};

			tx_fixed_link_clk: clock@3 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LINK_CLK>;
				clock-output-names = "tx_link_clk";
			};
		};

		axi_gpio: gpio@a4000000 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&versal_clk PMC_PL0_REF>;
			compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			interrupt-controller;
			interrupt-names = "ip2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 84 4>;
			reg = <0xa4000000 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x0>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x00000000>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x20>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};

		rx_dma: dma@bc420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc420000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		tx_dma: dma@bc430000  {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc430000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		axi_ad9081_core_rx: axi-ad9081-rx-hpc@a4a10000 {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0xa4a10000 0x8000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
		};

		axi_ad9081_core_tx: axi-ad9081-tx-hpc@a4b10000 {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0xa4b10000 0x4000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
		};

		axi_ad9081_rx_jesd: axi-jesd204-rx@a4a90000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0xa4a90000 0x1000>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 10>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;

			reset-done-gpios = <&axi_gpio 32 0>;
			pll-datapath-reset-gpios = <&axi_gpio 36 0>;
			datapath-reset-gpios = <&axi_gpio 38 0>;
		};

		axi_ad9081_tx_jesd: axi-jesd204-tx@a4b90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0xa4b90000 0x1000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 6>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;

			reset-done-gpios = <&axi_gpio 33 0>;
			pll-datapath-reset-gpios = <&axi_gpio 37 0>;
			datapath-reset-gpios = <&axi_gpio 39 0>;
		};

		axi_sysid_0: axi-sysid-0@a5000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0xa5000000 0x10000>;
		};
	};
};

&gic {
	num_cpus = <2>;
	num_interrupts = <96>;
};

&lpd_dma_chan0 {
	status = "okay";
};

&lpd_dma_chan1 {
	status = "okay";
};

&lpd_dma_chan2 {
	status = "okay";
};

&lpd_dma_chan3 {
	status = "okay";
};

&lpd_dma_chan4 {
	status = "okay";
};

&lpd_dma_chan5 {
	status = "okay";
};

&lpd_dma_chan6 {
	status = "okay";
};

&lpd_dma_chan7 {
	status = "okay";
};

&cci {
	status = "okay";
};

&smmu {
	status = "okay";
};

&i2c1 {
	status = "disabled";
};

&gpio1 {
	status = "okay";
};

&qspi {
	is-dual = <1>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};

&sdhci1 {
	clock-frequency = <199999985>;
	status = "okay";
};

&serial0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
};

&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&ttc0 {
	status = "okay";
};

&ref_clk {
	clock-frequency = <33333333>;
};

&gem0 {
	local-mac-address = [00 0a 35 ad 90 81];
};

&fpga_axi {
	axi_data_offload_tx: axi-data-offload-0@bc440000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc440000 0x10000>;
	};

	axi_data_offload_rx: axi-data-offload-1@bc450000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc450000 0x10000>;
	};
};

&axi_ad9081_core_tx {
	adi,axi-data-offload-connected = <&axi_data_offload_tx>;
	adi,axi-pl-fifo-enable;
};

#define fmc_spi spi0

&spi1 {
	status = "okay";

	hmc7044: hmc7044@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <0>;
		spi-max-frequency = <1000000>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-sysref-provider;

		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

		/*
		 * There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
		 * VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		 * VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		 * To determine which board is which, read the freqency printed on the VCXO
		 * or use the fru-dump utility:
		 * #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
		 */

		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
		//adi,vcxo-frequency = <122880000>;

		adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
		adi,pll1-ref-autorevert-enable;
		adi,vcxo-frequency = <100000000>;

		adi,pll1-loop-bandwidth-hz = <200>;
		adi,pll1-charge-pump-current-ua = <720>;
		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

		adi,pll2-output-frequency = <1500000000>;

		adi,sysref-timer-divider = <1024>;
		adi,pulse-generator-mode = <0>;

		adi,clkin0-buffer-mode  = <0x07>;
		adi,clkin1-buffer-mode  = <0x07>;
		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
		adi,gpo-controls = <0x37 0x33 0x00 0x00>;

		clock-output-names =
		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
		"hmc7044_out12", "hmc7044_out13";

		hmc7044_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS

		};

		hmc7044_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};

		hmc7044_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "CORE_CLK_TX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "FPGA_REFCLK1";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c10: channel@10 {
			reg = <10>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "FPGA_REFCLK";
			adi,divider = <8>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "FPGA_SYSREF";
			adi,divider = <768>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};
	};
};

&fmc_spi {

	trx0_ad9081: ad9081@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9082";
		reg = <0>;
		spi-max-frequency = <5000000>;

		/* Clocks */
		clocks = <&hmc7044 2>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		reset-gpios = <&axi_gpio 23 0>;
		sysref-req-gpios = <&axi_gpio 11 0>;
		rx2-enable-gpios = <&axi_gpio 25 0>;
		rx1-enable-gpios = <&axi_gpio 24 0>;
		tx2-enable-gpios = <&axi_gpio 27 0>;
		tx1-enable-gpios = <&axi_gpio 26 0>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

		jesd204-inputs =
		<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
		<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,dac-frequency-hz = /bits/ 64 <12000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <4>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};

				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
					adi,link-mode = <17>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3b>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,adc-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
					<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
					<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;

					adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
					adi,link-mode = <18>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */
				};
			};
		};

	};
};

Could you try this quickly let us know whether it will help anything?

-YH

Hey, sorry for the late response. I tried your updated device tree and jesd devices are failing to boot. Are there any other changes needed besides the device tree to change those clocks? Perhaps in the HDL? There are some jesd blocks in the design with lane rate parameters, I wasn't sure if I should meddle with them. I tried to and it didn't work for me anyway. Also, shouldn't those parameters at the top of the device tree be changed as well?:

/* RX path */
#define AD9081_RX_LANERATE_KHZ	24750000
#define AD9081_RX_LINK_CLK	375000000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	24750000
#define AD9081_TX_LINK_CLK	375000000

I would be happy to get some clarifications on the matter, Thank you very much!

OR1

Hey, a small extra update: it seems like the change that makes the jesd devices fail to load is adi,pll2-output-frequency from 3000000000 to 1500000000. So, I tried to keep it 3000000000 but multiply all the dividers by 2 instead. But now jesd_status is not proper:

The current device tree:

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/jesd204/adxcvr.h>

/include/ "system-conf.dtsi"

/* RX path */
#define AD9081_RX_LANERATE_KHZ	12375000
#define AD9081_RX_LINK_CLK	187500000

/* TX path */
#define AD9081_TX_LANERATE_KHZ	12375000
#define AD9081_TX_LINK_CLK	187500000

/ {
	model = "Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A";

	chosen {
		bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
		stdout-path = "serial0:115200";
	};

	fpga_axi: fpga-axi@0 {
		interrupt-parent = <&gic>;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;

		clocks {
			rx_fixed_linerate: clock@0 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LANERATE_KHZ>;
				clock-output-names = "rx_lane_clk";
			};

			tx_fixed_linerate: clock@1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LANERATE_KHZ>;
				clock-output-names = "tx_lane_clk";
			};

			rx_fixed_link_clk: clock@2 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_RX_LINK_CLK>;
				clock-output-names = "rx_link_clk";
			};

			tx_fixed_link_clk: clock@3 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <AD9081_TX_LINK_CLK>;
				clock-output-names = "tx_link_clk";
			};
		};

		axi_gpio: gpio@a4000000 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			clock-names = "s_axi_aclk";
			clocks = <&versal_clk PMC_PL0_REF>;
			compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			interrupt-controller;
			interrupt-names = "ip2intc_irpt";
			interrupt-parent = <&gic>;
			interrupts = <0 84 4>;
			reg = <0xa4000000 0x1000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,all-outputs = <0x0>;
			xlnx,all-outputs-2 = <0x0>;
			xlnx,dout-default = <0x00000000>;
			xlnx,dout-default-2 = <0x00000000>;
			xlnx,gpio-width = <0x20>;
			xlnx,gpio2-width = <0x20>;
			xlnx,interrupt-present = <0x1>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xFFFFFFFF>;
			xlnx,tri-default-2 = <0xFFFFFFFF>;
		};

		rx_dma: dma@bc420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc420000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		tx_dma: dma@bc430000  {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xbc430000 0x10000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&versal_clk PMC_PL1_REF>;
		};

		axi_ad9081_core_rx: axi-ad9081-rx-hpc@a4a10000 {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0xa4a10000 0x8000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
		};

		axi_ad9081_core_tx: axi-ad9081-tx-hpc@a4b10000 {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0xa4b10000 0x4000>;
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
		};

		axi_ad9081_rx_jesd: axi-jesd204-rx@a4a90000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0xa4a90000 0x1000>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 10>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;

			reset-done-gpios = <&axi_gpio 32 0>;
			pll-datapath-reset-gpios = <&axi_gpio 36 0>;
			datapath-reset-gpios = <&axi_gpio 38 0>;
		};

		axi_ad9081_tx_jesd: axi-jesd204-tx@a4b90000 {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0xa4b90000 0x1000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 6>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>;
			clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;

			reset-done-gpios = <&axi_gpio 33 0>;
			pll-datapath-reset-gpios = <&axi_gpio 37 0>;
			datapath-reset-gpios = <&axi_gpio 39 0>;
		};

		axi_sysid_0: axi-sysid-0@a5000000 {
			compatible = "adi,axi-sysid-1.00.a";
			reg = <0xa5000000 0x10000>;
		};
	};
};

&gic {
	num_cpus = <2>;
	num_interrupts = <96>;
};

&lpd_dma_chan0 {
	status = "okay";
};

&lpd_dma_chan1 {
	status = "okay";
};

&lpd_dma_chan2 {
	status = "okay";
};

&lpd_dma_chan3 {
	status = "okay";
};

&lpd_dma_chan4 {
	status = "okay";
};

&lpd_dma_chan5 {
	status = "okay";
};

&lpd_dma_chan6 {
	status = "okay";
};

&lpd_dma_chan7 {
	status = "okay";
};

&cci {
	status = "okay";
};

&smmu {
	status = "okay";
};

&i2c1 {
	status = "disabled";
};

&gpio1 {
	status = "okay";
};

&qspi {
	is-dual = <1>;
	num-cs = <1>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;
	status = "okay";
};

&sdhci1 {
	clock-frequency = <199999985>;
	status = "okay";
};

&serial0 {
	cts-override ;
	device_type = "serial";
	port-number = <0>;
};

&spi0 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&spi1 {
	is-decoded-cs = <0>;
	num-cs = <3>;
	status = "okay";
};

&ttc0 {
	status = "okay";
};

&ref_clk {
	clock-frequency = <33333333>;
};

&gem0 {
	local-mac-address = [00 0a 35 ad 90 81];
};

&fpga_axi {
	axi_data_offload_tx: axi-data-offload-0@bc440000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc440000 0x10000>;
	};

	axi_data_offload_rx: axi-data-offload-1@bc450000 {
		compatible = "adi,axi-data-offload-1.0.a";
		reg = <0xbc450000 0x10000>;
	};
};

&axi_ad9081_core_tx {
	adi,axi-data-offload-connected = <&axi_data_offload_tx>;
	adi,axi-pl-fifo-enable;
};

#define fmc_spi spi0

&spi1 {
	status = "okay";

	hmc7044: hmc7044@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,hmc7044";
		reg = <0>;
		spi-max-frequency = <1000000>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-sysref-provider;

		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */

		/*
		 * There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
		 * VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		 * VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		 * To determine which board is which, read the freqency printed on the VCXO
		 * or use the fru-dump utility:
		 * #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
		 */

		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
		//adi,vcxo-frequency = <122880000>;

		adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
		adi,pll1-ref-autorevert-enable;
		adi,vcxo-frequency = <100000000>;

		adi,pll1-loop-bandwidth-hz = <200>;
		adi,pll1-charge-pump-current-ua = <720>;
		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

		adi,pll2-output-frequency = <3000000000>;

		adi,sysref-timer-divider = <1024>;
		adi,pulse-generator-mode = <0>;

		adi,clkin0-buffer-mode  = <0x07>;
		adi,clkin1-buffer-mode  = <0x07>;
		adi,oscin-buffer-mode = <0x15>;

		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
		adi,gpo-controls = <0x37 0x33 0x00 0x00>;

		clock-output-names =
		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
		"hmc7044_out12", "hmc7044_out13";

		hmc7044_c0: channel@0 {
			reg = <0>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <16>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS

		};

		hmc7044_c2: channel@2 {
			reg = <2>;
			adi,extended-name = "DEV_REFCLK";
			adi,divider = <16>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "DEV_SYSREF";
			adi,divider = <1536>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};

		hmc7044_c6: channel@6 {
			reg = <6>;
			adi,extended-name = "CORE_CLK_TX";
			adi,divider = <16>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c8: channel@8 {
			reg = <8>;
			adi,extended-name = "FPGA_REFCLK1";
			adi,divider = <8>;	// 750
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c10: channel@10 {
			reg = <10>;
			adi,extended-name = "CORE_CLK_RX";
			adi,divider = <16>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "FPGA_REFCLK";
			adi,divider = <16>;	// 375
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
		};

		hmc7044_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "FPGA_SYSREF";
			adi,divider = <1536>;	// 3.90625
			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
			adi,jesd204-sysref-chan;
		};
	};
};

&fmc_spi {

	trx0_ad9081: ad9081@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9082";
		reg = <0>;
		spi-max-frequency = <5000000>;

		/* Clocks */
		clocks = <&hmc7044 2>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		reset-gpios = <&axi_gpio 23 0>;
		sysref-req-gpios = <&axi_gpio 11 0>;
		rx2-enable-gpios = <&axi_gpio 25 0>;
		rx1-enable-gpios = <&axi_gpio 24 0>;
		tx2-enable-gpios = <&axi_gpio 27 0>;
		tx1-enable-gpios = <&axi_gpio 26 0>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;

		jesd204-inputs =
		<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
		<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,dac-frequency-hz = /bits/ 64 <6000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};

				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; /* 100 MHz */
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <2>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
					adi,link-mode = <17>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3b>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;
			adi,adc-frequency-hz = /bits/ 64 <3000000000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};

				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <2>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};

				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
					<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
					<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>;

					adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
					adi,link-mode = <18>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */
					adi,converters-per-device = <4>;	/* JESD M */
					adi,octets-per-frame = <1>;		/* JESD F */
					adi,frames-per-multiframe = <256>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <8>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <1>;			/* JESD HD */
				};
			};
		};

	};
};

it seems like I'm missing a crucial step in configurating those clocks but I'm just not sure what. I also tried to configurate the Lane Rate in the Vivado design. this is my boot log:

root@xilinx-vpk120-20232:~# dmesg   
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083]
[    0.000000] Linux version 6.1.70adi-v2023.2 (oe-user@oe-host) (aarch64-xilinx-linux-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.39.0.20220819) #1 SMP Fri Oct 10 09:16:22 UTC 2025
[    0.000000] Machine model: Analog Devices AD9081-FMC-EBZ-VPK180 Rev.A
[    0.000000] earlycon: pl11 at MMIO32 0x00000000ff000000 (options '115200n8')
[    0.000000] printk: bootconsole [pl11] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000000000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x0000000a7fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000007fffffff]
[    0.000000]   node   0: [mem 0x0000000800000000-0x0000000a7fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000a7fffffff]
[    0.000000] cma: Reserved 256 MiB at 0x000000006d800000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 18 pages/cpu s36648 r8192 d28888 u73728
[    0.000000] pcpu-alloc: s36648 r8192 d28888 u73728 alloc=18*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-v2
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 3096576
[    0.000000] Kernel command line: console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[    0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 2.
[    0.000000] software IO TLB: mapped [mem 0x0000000069800000-0x000000006d800000] (64MB)
[    0.000000] Memory: 11967104K/12582912K available (18048K kernel code, 1822K rwdata, 12316K rodata, 2816K init, 682K bss, 353664K reserved, 262144K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 160 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000f9080000
[    0.000000] ITS: No ITS available, not enabling LPIs
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[    0.000000] sched_clock: 57 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[    0.008379] Console: colour dummy device 80x25
[    0.012870] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000)
[    0.023385] pid_max: default: 32768 minimum: 301
[    0.028197] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.035853] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.044336] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    0.050830] rcu: Hierarchical SRCU implementation.
[    0.055657] rcu:     Max phase no-delay instances is 1000.
[    0.061123] EFI services will not be available.
[    0.065768] smp: Bringing up secondary CPUs ...
[    0.070677] Detected PIPT I-cache on CPU1
[    0.070721] cacheinfo: Unable to detect cache hierarchy for CPU 1
[    0.070728] GICv3: CPU1: found redistributor 1 region 0:0x00000000f90a0000
[    0.070748] CPU1: Booted secondary processor 0x0000000001 [0x410fd083]
[    0.070796] smp: Brought up 1 node, 2 CPUs
[    0.098576] SMP: Total of 2 processors activated.
[    0.103310] CPU features: detected: 32-bit EL0 Support
[    0.108481] CPU features: detected: CRC32 instructions
[    0.113695] CPU: All CPU(s) started at EL2
[    0.117820] alternatives: applying system-wide alternatives
[    0.124169] devtmpfs: initialized
[    0.131798] Registered cp15_barrier emulation handler
[    0.136896] Registered setend emulation handler
[    0.141541] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.151365] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[    0.160612] DMI not present or invalid.
[    0.164769] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.171220] DMA: preallocated 2048 KiB GFP_KERNEL pool for atomic allocations
[    0.178598] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.186654] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.194757] audit: initializing netlink subsys (disabled)
[    0.200262] audit: type=2000 audit(0.132:1): state=initialized audit_enabled=0 res=1
[    0.208078] cpuidle: using governor menu
[    0.212088] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.218948] ASID allocator initialised with 65536 entries
[    0.224464] Serial: AMBA PL011 UART driver
[    0.230782] platform axi: Fixed dependency cycle(s) with /axi/interrupt-controller@f9000000
[    0.247086] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.253934] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.260245] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.267077] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.273386] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.280217] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.286527] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.293361] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.367710] raid6: neonx8   gen()  4131 MB/s
[    0.440048] raid6: neonx4   gen()  4044 MB/s
[    0.512382] raid6: neonx2   gen()  3367 MB/s
[    0.584714] raid6: neonx1   gen()  2433 MB/s
[    0.657054] raid6: int64x8  gen()  2334 MB/s
[    0.729393] raid6: int64x4  gen()  2270 MB/s
[    0.801733] raid6: int64x2  gen()  2210 MB/s
[    0.874077] raid6: int64x1  gen()  1687 MB/s
[    0.878378] raid6: using algorithm neonx8 gen() 4131 MB/s
[    0.951842] raid6: .... xor() 3033 MB/s, rmw enabled
[    0.956841] raid6: using neon recovery algorithm
[    0.961763] iommu: Default domain type: Translated 
[    0.966677] iommu: DMA domain TLB invalidation policy: strict mode 
[    0.973129] SCSI subsystem initialized
[    0.976913] libata version 3.00 loaded.
[    0.977009] usbcore: registered new interface driver usbfs
[    0.982550] usbcore: registered new interface driver hub
[    0.987908] usbcore: registered new device driver usb
[    0.993096] mc: Linux media interface: v0.10
[    0.997413] videodev: Linux video capture interface: v2.00
[    1.002969] pps_core: LinuxPPS API ver. 1 registered
[    1.007970] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.017169] PTP clock support registered
[    1.021129] EDAC MC: Ver: 3.0.0
[    1.024625] jesd204: created con: id=0, topo=0, link=0, /axi/spi@ff050000/hmc7044@0 <-> /fpga-axi@0/axi-jesd204-tx@a4b90000
[    1.035862] jesd204: created con: id=1, topo=0, link=2, /axi/spi@ff050000/hmc7044@0 <-> /fpga-axi@0/axi-jesd204-rx@a4a90000
[    1.047095] jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@a4b90000 <-> /fpga-axi@0/axi-ad9081-tx-hpc@a4b10000
[    1.059286] jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@a4a90000 <-> /fpga-axi@0/axi-ad9081-rx-hpc@a4a10000
[    1.071475] jesd204: created con: id=4, topo=0, link=2, /fpga-axi@0/axi-ad9081-rx-hpc@a4a10000 <-> /axi/spi@ff040000/ad9081@0
[    1.082875] jesd204: created con: id=5, topo=0, link=0, /fpga-axi@0/axi-ad9081-tx-hpc@a4b10000 <-> /axi/spi@ff040000/ad9081@0
[    1.094273] jesd204: /axi/spi@ff040000/ad9081@0: JESD204[0:2] transition uninitialized -> initialized
[    1.103567] jesd204: /axi/spi@ff040000/ad9081@0: JESD204[0:0] transition uninitialized -> initialized
[    1.112856] jesd204: found 6 devices and 1 topologies
[    1.117965] FPGA manager framework
[    1.121480] Advanced Linux Sound Architecture Driver Initialized.
[    1.127887] Bluetooth: Core ver 2.22
[    1.131495] NET: Registered PF_BLUETOOTH protocol family
[    1.136842] Bluetooth: HCI device and connection manager initialized
[    1.143238] Bluetooth: HCI socket layer initialized
[    1.148149] Bluetooth: L2CAP socket layer initialized
[    1.153242] Bluetooth: SCO socket layer initialized
[    1.158513] clocksource: Switched to clocksource arch_sys_counter
[    1.164783] VFS: Disk quotas dquot_6.6.0
[    1.168762] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.179161] NET: Registered PF_INET protocol family
[    1.184396] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    1.198996] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear)
[    1.207766] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    1.215578] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    1.224298] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
[    1.232839] TCP: Hash tables configured (established 131072 bind 65536)
[    1.239578] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear)
[    1.246651] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear)
[    1.254221] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    1.260242] RPC: Registered named UNIX socket transport module.
[    1.266212] RPC: Registered udp transport module.
[    1.270945] RPC: Registered tcp transport module.
[    1.275678] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.282495] PCI: CLS 0 bytes, default 64
[    1.286656] Trying to unpack rootfs image as initramfs...
[    1.292993] Initialise system trusted keyrings
[    1.297571] workingset: timestamp_bits=46 max_order=22 bucket_order=0
[    1.304859] NFS: Registering the id_resolver key type
[    1.309981] Key type id_resolver registered
[    1.314201] Key type id_legacy registered
[    1.318267] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    1.325039] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    1.332523] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    1.339834] fuse: init (API version 7.37)
[    1.371711] NET: Registered PF_ALG protocol family
[    1.376553] xor: measuring software checksum speed
[    1.382835]    8regs           :  6785 MB/sec
[    1.388561]    32regs          :  7343 MB/sec
[    1.394595]    arm64_neon      :  5990 MB/sec
[    1.398985] xor: using function: 32regs (7343 MB/sec)
[    1.404085] Key type asymmetric registered
[    1.408225] Asymmetric key parser 'x509' registered
[    1.413193] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    1.420655] io scheduler mq-deadline registered
[    1.425220] io scheduler kyber registered
[    1.452359] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.459497] Serial: AMBA driver
[    1.463212] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    1.472454] brd: module loaded
[    1.477654] loop: module loaded
[    1.481207] Freeing initrd memory: 5336K
[    1.481535] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.493601] tun: Universal TUN/TAP device driver, 1.6
[    1.498795] CAN device driver interface
[    1.502955] SPI driver wl1271_spi has no spi_device_id for ti,wl1271
[    1.509356] SPI driver wl1271_spi has no spi_device_id for ti,wl1273
[    1.515754] SPI driver wl1271_spi has no spi_device_id for ti,wl1281
[    1.522154] SPI driver wl1271_spi has no spi_device_id for ti,wl1283
[    1.528548] SPI driver wl1271_spi has no spi_device_id for ti,wl1285
[    1.534945] SPI driver wl1271_spi has no spi_device_id for ti,wl1801
[    1.541343] SPI driver wl1271_spi has no spi_device_id for ti,wl1805
[    1.547739] SPI driver wl1271_spi has no spi_device_id for ti,wl1807
[    1.554133] SPI driver wl1271_spi has no spi_device_id for ti,wl1831
[    1.560534] SPI driver wl1271_spi has no spi_device_id for ti,wl1835
[    1.566931] SPI driver wl1271_spi has no spi_device_id for ti,wl1837
[    1.573402] usbcore: registered new interface driver asix
[    1.578866] usbcore: registered new interface driver ax88179_178a
[    1.585016] usbcore: registered new interface driver cdc_ether
[    1.590896] usbcore: registered new interface driver net1080
[    1.596611] usbcore: registered new interface driver cdc_subset
[    1.602587] usbcore: registered new interface driver zaurus
[    1.608220] usbcore: registered new interface driver cdc_ncm
[    1.613929] usbcore: registered new interface driver r8153_ecm
[    1.620298] usbcore: registered new interface driver uas
[    1.625671] usbcore: registered new interface driver usb-storage
[    1.631772] usbcore: registered new interface driver usbserial_generic
[    1.638352] usbserial: USB Serial support registered for generic
[    1.644414] usbcore: registered new interface driver ftdi_sio
[    1.650207] usbserial: USB Serial support registered for FTDI USB Serial Device
[    1.657580] usbcore: registered new interface driver upd78f0730
[    1.663545] usbserial: USB Serial support registered for upd78f0730
[    1.670301] SPI driver ads7846 has no spi_device_id for ti,tsc2046
[    1.676528] SPI driver ads7846 has no spi_device_id for ti,ads7843
[    1.682755] SPI driver ads7846 has no spi_device_id for ti,ads7845
[    1.688979] SPI driver ads7846 has no spi_device_id for ti,ads7873
[    1.695285] i2c_dev: i2c /dev entries driver
[    1.700562] usbcore: registered new interface driver uvcvideo
[    1.706975] Bluetooth: HCI UART driver ver 2.3
[    1.711453] Bluetooth: HCI UART protocol H4 registered
[    1.716626] Bluetooth: HCI UART protocol BCSP registered
[    1.721982] Bluetooth: HCI UART protocol LL registered
[    1.727162] Bluetooth: HCI UART protocol ATH3K registered
[    1.732602] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    1.738935] Bluetooth: HCI UART protocol Intel registered
[    1.744383] Bluetooth: HCI UART protocol QCA registered
[    1.749661] usbcore: registered new interface driver bcm203x
[    1.755377] usbcore: registered new interface driver bpa10x
[    1.761003] usbcore: registered new interface driver bfusb
[    1.766539] usbcore: registered new interface driver btusb
[    1.772083] usbcore: registered new interface driver ath3k
[    1.777710] EDAC ZynqMP-OCM: ECC not enabled - Disabling EDAC driver
[    1.784329] sdhci: Secure Digital Host Controller Interface driver
[    1.790563] sdhci: Copyright(c) Pierre Ossman
[    1.794949] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.800832] ledtrig-cpu: registered to indicate activity on CPUs
[    1.806927] SMCCC: SOC_ID: ID = jep106:0049:0000 Revision = 0x00000000
[    1.813576] zynqmp_firmware_probe Platform Management API v1.0
[    1.819508] zynqmp_firmware_probe Trustzone version v1.0
[    1.825315] xlnx_event_manager xlnx_event_manager: SGI 15 Registered over TF-A
[    1.832605] xlnx_event_manager xlnx_event_manager: Xilinx Event Management driver probed
[    1.889374] zynqmp-aes zynqmp-aes.0: AES is not supported on the platform
[    1.896310] zynqmp_rsa zynqmp_rsa.0: RSA is not supported on the platform
[    1.903238] usbcore: registered new interface driver usbhid
[    1.908849] usbhid: USB HID core driver
[    1.912815] SPI driver fb_seps525 has no spi_device_id for syncoam,seps525
[    1.922437] SPI driver adis16475 has no spi_device_id for adi,adis16470
[    1.929118] SPI driver adis16475 has no spi_device_id for adi,adis16475-1
[    1.935962] SPI driver adis16475 has no spi_device_id for adi,adis16475-2
[    1.942797] SPI driver adis16475 has no spi_device_id for adi,adis16475-3
[    1.949628] SPI driver adis16475 has no spi_device_id for adi,adis16477-1
[    1.956466] SPI driver adis16475 has no spi_device_id for adi,adis16477-2
[    1.963296] SPI driver adis16475 has no spi_device_id for adi,adis16477-3
[    1.970133] SPI driver adis16475 has no spi_device_id for adi,adis16465-1
[    1.976966] SPI driver adis16475 has no spi_device_id for adi,adis16465-2
[    1.983801] SPI driver adis16475 has no spi_device_id for adi,adis16465-3
[    1.990637] SPI driver adis16475 has no spi_device_id for adi,adis16467-1
[    1.997477] SPI driver adis16475 has no spi_device_id for adi,adis16467-2
[    2.004308] SPI driver adis16475 has no spi_device_id for adi,adis16467-3
[    2.011143] SPI driver adis16475 has no spi_device_id for adi,adis16500
[    2.017801] SPI driver adis16475 has no spi_device_id for adi,adis16501
[    2.024459] SPI driver adis16475 has no spi_device_id for adi,adis16505-1
[    2.031300] SPI driver adis16475 has no spi_device_id for adi,adis16505-2
[    2.038133] SPI driver adis16475 has no spi_device_id for adi,adis16505-3
[    2.044973] SPI driver adis16475 has no spi_device_id for adi,adis16507-1
[    2.051812] SPI driver adis16475 has no spi_device_id for adi,adis16507-2
[    2.058647] SPI driver adis16475 has no spi_device_id for adi,adis16507-3
[    2.065485] SPI driver adis16475 has no spi_device_id for adi,adis16575-2
[    2.072320] SPI driver adis16475 has no spi_device_id for adi,adis16575-3
[    2.079158] SPI driver adis16475 has no spi_device_id for adi,adis16576-2
[    2.085994] SPI driver adis16475 has no spi_device_id for adi,adis16576-3
[    2.092829] SPI driver adis16475 has no spi_device_id for adi,adis16577-2
[    2.099663] SPI driver adis16475 has no spi_device_id for adi,adis16577-3
[    2.107259] ARM CCI_500 PMU driver probed
[    2.107368] axi_sysid a5000000.axi-sysid-0: AXI System ID core version (1.01.a) found
[    2.119452] axi_sysid a5000000.axi-sysid-0: [ad9082_fmca_ebz] on [vpk180] git branch <hdl_2023_r2> git <d146370c10fdd55156de2bafdd9b24292c01b6e1> clean [2025-06-30 06:41:03] UTC
[    2.135685] fpga_manager fpga0: Xilinx Versal FPGA Manager registered
[    2.143022] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    2.151728] Initializing XFRM netlink socket
[    2.156078] NET: Registered PF_INET6 protocol family
[    2.161482] Segment Routing with IPv6
[    2.165194] In-situ OAM (IOAM) with IPv6
[    2.169203] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    2.175421] NET: Registered PF_PACKET protocol family
[    2.180518] NET: Registered PF_KEY protocol family
[    2.185426] can: controller area network core
[    2.189836] NET: Registered PF_CAN protocol family
[    2.194658] can: raw protocol
[    2.197641] can: broadcast manager protocol
[    2.201854] can: netlink gateway - max_hops=1
[    2.206316] Bluetooth: RFCOMM TTY layer initialized
[    2.211236] Bluetooth: RFCOMM socket layer initialized
[    2.216420] Bluetooth: RFCOMM ver 1.11
[    2.220197] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.225543] Bluetooth: BNEP filters: protocol multicast
[    2.230802] Bluetooth: BNEP socket layer initialized
[    2.235801] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.241766] Bluetooth: HIDP socket layer initialized
[    2.246880] 9pnet: Installing 9P2000 support
[    2.251205] NET: Registered PF_IEEE802154 protocol family
[    2.256661] Key type dns_resolver registered
[    2.261172] registered taskstats version 1
[    2.265298] Loading compiled-in X.509 certificates
[    2.271933] Btrfs loaded, crc32c=crc32c-generic, zoned=no, fsverity=no
[    2.500882] ff000000.serial: ttyAMA0 at MMIO 0xff000000 (irq = 17, base_baud = 0) is a PL011 rev3
[    2.509846] printk: console [ttyAMA0] enabled
[    2.518578] printk: bootconsole [pl11] disabled
[    2.527967] gpio gpiochip0: (a4000000.gpio): not an immutable chip, please consider fixing it!
[    2.536772] of-fpga-region fpga: FPGA Region probed
[    2.630654] hmc7044 spi2.0: PLL1: Locked, CLKIN0 @ 100000000 Hz, PFD: 1000 kHz - PLL2: Locked @ 3000.000000 MHz
[    2.640985] jesd204: /axi/spi@ff050000/hmc7044@0,jesd204:1,parent=spi2.0: Using as SYSREF provider
[    2.650311] spi_master spi0: /axi/spi@f1030000/flash@0 has no valid 'reg' property (2)
[    2.658486] macb ff0c0000.ethernet: Not enabling partial store and forward
[    2.667255] macb ff0c0000.ethernet eth0: Cadence GEM rev 0x0107010b at 0xff0c0000 irq 34 (00:0a:35:ad:90:81)
[    2.738682] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    2.744178] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    2.751899] xhci-hcd xhci-hcd.0.auto: USB3 root hub has no ports
[    2.757901] xhci-hcd xhci-hcd.0.auto: hcc params 0x0238fe65 hci version 0x110 quirks 0x0000000000010810
[    2.767310] xhci-hcd xhci-hcd.0.auto: irq 35, io mem 0xfe200000
[    2.773364] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.01
[    2.781630] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.788846] usb usb1: Product: xHCI Host Controller
[    2.793718] usb usb1: Manufacturer: Linux 6.1.70adi-v2023.2 xhci-hcd
[    2.800071] usb usb1: SerialNumber: xhci-hcd.0.auto
[    2.805308] hub 1-0:1.0: USB hub found
[    2.809074] hub 1-0:1.0: 1 port detected
[    2.813773] rtc_zynqmp f12a0000.rtc: registered as rtc0
[    2.819014] rtc_zynqmp f12a0000.rtc: setting system clock to 2025-12-14T16:16:31 UTC (1765728991)
[    2.828329] cdns-i2c ff020000.i2c: 100 kHz mmio ff020000 irq 38
[    2.834754] cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 1399999 KHz, changing to: 1199999 KHz
[    2.846697] axi-jesd204-rx a4a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0xA4A90000. Encoder 64b66b, width 8/8, lanes 8, jesd204-fsm.
[    2.859616] axi-jesd204-tx a4b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0xA4B90000. Encoder 64b66b, width 8/8, lanes 8, jesd204-fsm.
[    2.872579] ad9081 spi1.0: supply vdd not found, using dummy regulator
[    2.877652] mmc0: SDHCI controller on f1050000.mmc [f1050000.mmc] using ADMA 64-bit
[    2.921831] mmc0: new high speed SDHC card at address aaaa
[    2.927647] mmcblk0: mmc0:aaaa SE32G 29.7 GiB 
[    2.934932]  mmcblk0: p1 p2
[    4.810257] ad9081 spi1.0: AD9082 Rev. 3 Grade 2 (API 1.6.0) probed
[    4.836905] iio_dmaengine_buffer_alloc:231 width 0 (DMA width >= 256-bits ?)
[    4.844856] cf_axi_adc a4a10000.axi-ad9081-rx-hpc: ADI AIM (10.03.) at 0xA4A10000 mapped to 0x(____ptrval____) probed ADC AD9081 as MASTER
[    4.874552] iio_dmaengine_buffer_alloc:231 width 0 (DMA width >= 256-bits ?)
[    4.881978] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed
[    4.892680] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed
[    4.903380] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> initialized
[    4.914073] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> initialized
[    4.924768] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed
[    4.935464] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed
[    4.946158] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle
[    4.956244] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle
[    4.966330] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init
[    4.976853] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init
[    4.987376] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init
[    4.998331] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init
[    5.009291] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported
[    5.020505] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported
[    5.032034] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
[    5.041035] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup
[    5.052688] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup
[    5.076617] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
[    5.088355] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
[    5.100091] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
[    5.111912] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
[    5.123736] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
[    5.135559] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
[    5.275760] axi-jesd204-tx a4b90000.axi-jesd204-tx: Waiting for tx_pll_datapath_reset_done timedout (0)
[    5.285150] jesd204: /fpga-axi@0/axi-jesd204-tx@a4b90000,jesd204:5,parent=a4b90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -110
[    5.298535] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: Rolling back from 'clk_sync_stage3', got error -110
[    5.309751] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup
[    5.321141] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup
[    5.332530] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> clk_sync_stage3
[    5.343916] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> clk_sync_stage3
[    5.355306] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
[    5.367127] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
[    5.378952] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
[    5.390774] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
[    5.402596] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
[    5.414330] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
[    5.426065] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> link_supported
[    5.437712] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> link_supported
[    5.449363] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_init
[    5.460576] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_init
[    5.471790] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> device_init
[    5.482743] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> device_init
[    5.493697] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> idle
[    5.504216] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> idle
[    5.514739] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> initialized
[    5.525259] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> initialized
[    5.535779] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed
[    5.546471] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed
[    5.557165] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle
[    5.567250] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle
[    5.577338] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init
[    5.587857] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init
[    5.598377] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init
[    5.609330] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init
[    5.620288] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported
[    5.631502] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported
[    5.643026] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup
[    5.654677] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup
[    5.678602] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
[    5.690340] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
[    5.702075] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
[    5.713897] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
[    5.725720] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
[    5.737540] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
[    5.877736] axi-jesd204-tx a4b90000.axi-jesd204-tx: Waiting for tx_pll_datapath_reset_done timedout (0)
[    5.887125] jesd204: /fpga-axi@0/axi-jesd204-tx@a4b90000,jesd204:5,parent=a4b90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -110
[    5.900509] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: Rolling back from 'clk_sync_stage3', got error -110
[    5.911726] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup
[    5.923114] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup
[    5.934501] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> clk_sync_stage3
[    5.945890] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> clk_sync_stage3
[    5.957280] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
[    5.969101] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
[    5.980925] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
[    5.992747] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
[    6.004569] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
[    6.016303] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
[    6.028040] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> link_supported
[    6.039690] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> link_supported
[    6.051339] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_init
[    6.062552] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_init
[    6.073767] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> device_init
[    6.084720] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> device_init
[    6.095673] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> idle
[    6.106194] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> idle
[    6.116717] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> initialized
[    6.127236] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> initialized
[    6.137756] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed
[    6.148448] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed
[    6.159141] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle
[    6.169228] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle
[    6.179315] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init
[    6.189834] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init
[    6.200354] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init
[    6.211306] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init
[    6.222264] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported
[    6.233480] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported
[    6.245002] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup
[    6.256653] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup
[    6.280580] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
[    6.292319] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
[    6.304055] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.315874] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.327696] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
[    6.339517] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
[    6.479773] axi-jesd204-tx a4b90000.axi-jesd204-tx: Waiting for tx_pll_datapath_reset_done timedout (0)
[    6.489164] jesd204: /fpga-axi@0/axi-jesd204-tx@a4b90000,jesd204:5,parent=a4b90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -110
[    6.502548] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: Rolling back from 'clk_sync_stage3', got error -110
[    6.513765] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup
[    6.525154] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup
[    6.536542] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> clk_sync_stage3
[    6.547928] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> clk_sync_stage3
[    6.559319] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
[    6.571141] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
[    6.582965] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
[    6.594787] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
[    6.606609] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
[    6.618343] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
[    6.630079] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> link_supported
[    6.641725] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> link_supported
[    6.653376] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_init
[    6.664590] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_init
[    6.675804] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> device_init
[    6.686756] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> device_init
[    6.697710] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> idle
[    6.708229] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> idle
[    6.718753] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> initialized
[    6.729272] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> initialized
[    6.739792] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed
[    6.750485] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed
[    6.761178] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle
[    6.771263] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle
[    6.781351] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init
[    6.791870] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init
[    6.802390] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init
[    6.813343] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init
[    6.824301] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported
[    6.835514] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported
[    6.847040] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup
[    6.858690] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup
[    6.882615] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
[    6.894352] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
[    6.906088] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.917910] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.929732] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
[    6.941551] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
[    7.081745] axi-jesd204-tx a4b90000.axi-jesd204-tx: Waiting for tx_pll_datapath_reset_done timedout (0)
[    7.091135] jesd204: /fpga-axi@0/axi-jesd204-tx@a4b90000,jesd204:5,parent=a4b90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -110
[    7.104519] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: Rolling back from 'clk_sync_stage3', got error -110
[    7.115738] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup
[    7.127125] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup
[    7.138513] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> clk_sync_stage3
[    7.149899] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> clk_sync_stage3
[    7.161289] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
[    7.173110] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
[    7.184935] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
[    7.196756] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
[    7.208579] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
[    7.220313] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
[    7.232048] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> link_supported
[    7.243697] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> link_supported
[    7.255347] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_init
[    7.266560] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_init
[    7.277774] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> device_init
[    7.288727] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> device_init
[    7.299681] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> idle
[    7.310202] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> idle
[    7.320721] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: FSM completed with error -110
[    7.330028] cf_axi_dds a4b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0xA4B10000 mapped to 0x(____ptrval____), probed DDS AD9081
[    7.346148] of_cfs_init
[    7.348624] of_cfs_init: OK
[    7.351469] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    7.379789] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    7.386750] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[    7.394871] clk: Not disabling unused clocks
[    7.399508] ALSA device list:
[    7.402467]   No soundcards found.
[    7.406131] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    7.414747] cfg80211: failed to load regulatory.db
[    7.419540] uart-pl011 ff000000.serial: no DMA platform data
[    7.425943] Freeing unused kernel memory: 2816K
[    7.442566] Run /init as init process
[    7.446218]   with arguments:
[    7.446221]     /init
[    7.446223]   with environment:
[    7.446225]     HOME=/
[    7.446227]     TERM=linux
[    9.568438] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Quota mode: none.
[    9.983874] systemd[1]: systemd 251.8+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTS
ETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -TPM2 -BZIP2 -LZ4 -XZ -ZLIB +ZSTD -BPF_FRAMEWORK +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid)
[   10.015628] systemd[1]: Detected architecture arm64.
[   10.087766] systemd[1]: Hostname set to <xilinx-vpk120-20232>.
[   10.191586] systemd-sysv-generator[310]: SysV service '/etc/init.d/inetd.busybox' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a n
ative systemd unit file, in order to make it more safe and robust.
[   10.215962] systemd-sysv-generator[310]: SysV service '/etc/init.d/nfsserver' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a nativ
e systemd unit file, in order to make it more safe and robust.
[   10.241655] systemd-sysv-generator[310]: SysV service '/etc/init.d/sshd' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native sys
temd unit file, in order to make it more safe and robust.
[   10.478313] systemd[1]: Queued start job for default target Multi-User System.
[   10.513340] systemd[1]: Created slice Slice /system/getty.
[   10.535662] systemd[1]: Created slice Slice /system/modprobe.
[   10.555530] systemd[1]: Created slice Slice /system/serial-getty.
[   10.575312] systemd[1]: Created slice User and Session Slice.
[   10.594730] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[   10.618688] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[   10.642705] systemd[1]: Reached target Path Units.
[   10.658605] systemd[1]: Reached target Remote File Systems.
[   10.678592] systemd[1]: Reached target Slice Units.
[   10.694594] systemd[1]: Reached target Swaps.
[   10.710977] systemd[1]: Listening on RPCbind Server Activation Socket.
[   10.730752] systemd[1]: Reached target RPC Port Mapper.
[   10.753142] systemd[1]: Listening on Syslog Socket.
[   10.770751] systemd[1]: Listening on initctl Compatibility Named Pipe.
[   10.790925] systemd[1]: Listening on Journal Audit Socket.
[   10.810810] systemd[1]: Listening on Journal Socket (/dev/log).
[   10.830860] systemd[1]: Listening on Journal Socket.
[   10.850932] systemd[1]: Listening on Network Service Netlink Socket.
[   10.870903] systemd[1]: Listening on udev Control Socket.
[   10.890776] systemd[1]: Listening on udev Kernel Socket.
[   10.910821] systemd[1]: Listening on User Database Manager Socket.
[   10.950770] systemd[1]: Mounting Huge Pages File System...
[   10.972625] systemd[1]: Mounting POSIX Message Queue File System...
[   10.996662] systemd[1]: Mounting Kernel Debug File System...
[   11.014792] systemd[1]: Kernel Trace File System was skipped because of a failed condition check (ConditionPathExists=/sys/kernel/tracing).
[   11.031682] systemd[1]: Mounting Temporary Directory /tmp...
[   11.053448] systemd[1]: Create List of Static Device Nodes was skipped because of a failed condition check (ConditionFileNotEmpty=/lib/modules/6.1.70adi-v2023.2/modules.devname).
[   11.086879] systemd[1]: Starting Load Kernel Module configfs...
[   11.108810] systemd[1]: Starting Load Kernel Module drm...
[   11.128921] systemd[1]: Starting Load Kernel Module fuse...
[   11.166894] systemd[1]: Starting RPC Bind...
[   11.182664] systemd[1]: File System Check on Root Device was skipped because of a failed condition check (ConditionPathIsReadWrite=!/).
[   11.195381] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
[   11.208267] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
[   11.219441] systemd[1]: Starting Journal Service...
[   11.231888] systemd[1]: Load Kernel Modules was skipped because all trigger condition checks failed.
[   11.258825] systemd[1]: Mounting NFSD configuration filesystem...
[   11.284806] systemd[1]: Starting Generate network units from Kernel command line...
[   11.306955] systemd[1]: Starting Remount Root and Kernel File Systems...
[   11.328662] systemd[1]: Starting Apply Kernel Variables...
[   11.340803] EXT4-fs (mmcblk0p2): re-mounted. Quota mode: none.
[   11.361324] systemd[1]: Starting Coldplug All udev Devices...
[   11.386255] systemd[1]: Started RPC Bind.
[   11.406928] systemd[1]: Started Journal Service.
[   11.736063] systemd-journald[319]: Received client request to flush runtime journal.
[   12.810537] random: crng init done
[   13.088715] macb ff0c0000.ethernet eth0: PHY [ff0c0000.ethernet-ffffffff:01] driver [TI DP83867] (irq=POLL)
[   13.098504] macb ff0c0000.ethernet eth0: configuring for phy/rgmii-id link mode
[   13.128108] pps pps0: new PPS source ptp0
[   13.139669] macb ff0c0000.ethernet: gem-ptp-timer ptp clock registered.
[   15.489025] audit: type=1006 audit(1765729004.164:2): pid=667 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=1 res=1
[   15.501311] audit: type=1300 audit(1765729004.164:2): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffeb9bd710 a2=1 a3=1 items=0 ppid=1 pid=667 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 f
sgid=0 tty=(none) ses=1 comm="(systemd)" exe="/lib/systemd/systemd" key=(null)
[   15.526608] audit: type=1327 audit(1765729004.164:2): proctitle="(systemd)"
[   17.227855] macb ff0c0000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[   17.235544] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   18.360332] systemd-journald[319]: Time jumped backwards, rotating.
[   37.368980] audit: type=1006 audit(1765729025.327:3): pid=686 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=2 res=1
[   37.381543] audit: type=1300 audit(1765729025.327:3): arch=c00000b7 syscall=64 success=yes exit=4 a0=8 a1=ffffeb9bd710 a2=4 a3=1 items=0 ppid=1 pid=686 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=
0 fsgid=0 tty=(none) ses=2 comm="(systemd)" exe="/lib/systemd/systemd" key=(null)
[   37.407097] audit: type=1327 audit(1765729025.327:3): proctitle="(systemd)"
[   38.121759] audit: type=1006 audit(1765729026.079:4): pid=683 uid=0 old-auid=4294967295 auid=1000 tty=(none) old-ses=4294967295 ses=3 res=1
[   38.134307] audit: type=1300 audit(1765729026.079:4): arch=c00000b7 syscall=64 success=yes exit=4 a0=7 a1=ffffe07fc820 a2=4 a3=1 items=0 ppid=1 pid=683 auid=1000 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=
0 fsgid=0 tty=(none) ses=3 comm="sshd" exe="/usr/sbin/sshd" key=(null)
[   38.158912] audit: type=1327 audit(1765729026.079:4): proctitle=737368643A20616E616C6F67205B707269765D
root@xilinx-vpk120-20232:~# 

Thank you for your continued support!

Hey there, I just wanted to ask - is this still being looked at? Is there any info I can provide to help? 

OR1

Hey, I got one more update:
I was able to make it work, apparently I had some of the pins wired wrong. Now the design runs successfully on 12.375Ghz lane rate and I am able too see output from the DAC. Currently the output is not as expected (for example, seeing a lot of noise and spikes when transmitting a single tone CW with DDS), but I would like to investigate the matter more thoroughly before approaching your team for support. Thank you very much for the help!