Instantaneous bandwidth

Hello,

As you can find in the AD9988 datasheet 

► The maximum transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R, =1.5GHz FDUC/FDDC BW *0.8)

► RF DAC/RF ADC RF frequency range (-3dB Analog roll off) up to 7.5 GHz

So the application for +/-500MHz at 4.8GHz is okay with AD9988. 

Please make sure

• iBW/DAC dependency : bandwidth (iBW) per channel is based on the lane rate, the input data rate, level of interpolation used, resolution of the sample, type of serial interface(Encode ratio for 204B/C), number of DACs enabled, DAC update rate, filter bandwidth coefficient(0.8)

• iBW/ADC dependency : Instantaneous bandwidth (iBW) per channel is based on the ADC sampling rate, level of decimation used, and filter bandwidth coefficient(0.814)

Thanks

Hello THA , Thank you for the clarification. I have som queries.

1. How it is possible to generate baseband IQ data for +-500MHz bandwidth. Because in FPGA for jesd204B with max lane rate=15Gbps, Tx_global_clk= lane rate/40= 15Gbps/40=375 MHz. So tx_global_clk is less than bandwidth of +-500 MHz, then how we can generate baseband IQ data at 1GHz using tx_global_clk. Also is this possible with zcu102 board. Is FPGA supports this much of clock speed on PL side?

2. Another confusion is do I need to give I data to on chip DAC0 and Q data to on chip DAC1 or Can I give IQ data  common to DAC0 only and it will internally generate DAC0 RF output.

3. Also with on chip ADC0 is it will give IQ data with respective to ADC0 only.

Thanks 

Hello, Thanks for the detailed clarification. So as you said iBW=data rate* 0.8 then as per example 14 in ug1578 : For JESD204C

Lane rate= (M/L)*NP*(66/64)*data rate

16.5 Gbps = (8/8)*16*1.03125*data rate

data rate=1Gsps

iBW= 1Gsps * 0.8= 800MHz, is this calculations are correct. 

Thanks

Hello, thank you for replying. As you said max lane rate for JESD204B is 12.5Gbps, but as per following link and image it is mentioned as 15.5 Gbps on zcu102. So still I am confused what is the actual speed for JESD204B/C on zcu102. Also which example number from ug1578 user guide is suitable for my requirement of iBW = 700MHz on all channels. I think example 14 is suitable for my case, but also tell your suggestions.

https://analogdevicesinc.github.io/hdl/projects/ad9081_fmca_ebz/index.htm

Thanks 

Hello THA , still I need more clarification on my second point:

As I have gone through ug1578 figure 75 to 85, but still I am not able to get the logic. As in figure from 79 to 85 it is showing that two different DAC's are needed for I data and Q data inputs, so at the output of DAC0 we will get I RF output and DAC1 we will get Q RF output, is this my assumption is correct or wrong, please clarify this. Also for direct RF sampling DAC mixing of I and Q signal is done internally and it gives single RF output, am I right?

So is this means I cant mix IQ signal internally and get one single RF output on one of DAC.?

Please check the following figures and clarify my above doubts. Because its very confusing and quite tricky to understand , so better way you explain me correct approach.

Thanks

Thank you for pointing that. Even though the max lane rate of JESD204B is 12.5GHz, ADI JESD IP and converters allow higher speed, so it would be 16 Gbps for both of 204B and 204C with ZCU102.

Hello THA , Please clarify this asap, waiting for your answer. Your response will help me for taking quick decision, whether this device suits for our application or not. 

Thank you 

Complex signal is used for quadrature mixer, and only I signal out of quadrature mixer is sent to the DAC at the end. There is no need to mix I and Q internally to convert the signal into analog domain. If you want to use external quadrature mixer that require complex signal (for further upconversion), then you need to send I to one DAC and Q signal to another DAC.

Hope that helps.

-YH

Hello, yhkim thank you for the clarification. So you mean to say I have to give IQ complex signal from FPGA to ad9988 and after that on chip ad9988 quadrature mixer will mix IQ signal and it will give single RF Output through DAC. So based on this approach will it be any limitations on instantaneous bandwidth of ad9988? In that case can I achieve same +-500MHz bandwidth centre at 4.8GHz? And the same I want to generate RF output on all 4 DAC's simultaneously.

Thank you 

Yes, it is possible. You need 1.25 GSPS to achieve 1 GHz IBW. If you plan to use ZCU102 for this purpose, you need to find a configuration with NP=12 in order to the keep the lane rate lower than maximum supported by ZCU102.

Lane rate= (M/L)*NP*(66/64)*data rate => (8/8)*12*(66/64)*1.25GSPS => 15.46 Gbps.

-YH

Hello yhkim , thank you for the reply. But for zcu102 there are 4 lanes for Tx and 4 lanes for Rx. So accordingly we need to take L=4 for tx side and L=4 for Rx side. For jesd204c calculation: max lane rate supported is 16.5 Gbps on zcu102 according to GTH transceiver speed

Lane rate= (M/L)*NP*(66/64)*data rate

16.5 Gbps= (8/4)*12*1.03125*data rate

data rate= 666.66 Msps

iBW= 666.66 Msps * 0.8= 533.328MHz

Still I am not achieving 1Ghz bandwidth with zcu102 board because of 4 lanes on tx side and 4 lanes on rx side. If we increase lanes then I think it is possible. But unfortunately there is no option to increase lanes on zcu102 board I think so.

ADI's JESD IP implemented on ZCU102 supports up to 8 lanes of TX and 8 lanes of RX simultaneously.

-YH

ADI's JESD IP implemented on ZCU102 supports up to 8 lanes of TX and 8 lanes of RX simultaneously.

-YH

Hello yhkim ,

Thank you for clarification. 

Also why we need to take M=8 for tx and M=8 for Rx, even though the actual DAC's are 4 and ADC's are 4. Can I take M=4 with all 4 DAC' and 4 ADC's should work simultaneously?

Hi, each of ADC and DAC requires a pair of I and Q data stream in this case, and each stream is mapped to one virtual converter. So you need 8 virtual converters (M=8) for four pairs of data stream to work with four physical converters.

-YH

Hello yhkim ,

Thank you I got your point. And if I want to send only real data to DAC0, DAC1, DAC2, and DAC3 in that case M=8 or 4 ? Because I want four different signals on each DAC's simultaneously, not like signal1 I is on DAC0 and signal1 Q is on DAC1.What are the changes should I done in baremetal and hdl code? Also with only real data is it possible to achieve full +- 500 MHz bandwidth?

Thank you 

if you really want to use real only mode, then yes you can use all four DACs independently with M=4 using the full bandwidth mode (interpolation =1). And you can defnitely achieve IBW over 1GHz but you need to double the sample rate to realize the same IBW compared to complex mode, and in fact the minimum IBW  you can implement would be higher than 1GHz becuase the minimum DAC clock should be higher than 2.5 GHz. Please refer to the user guide and data sheet for more details about the full bandwith mode and clock limitation.

-YH