Sync toggling on logic device JESD204B TX to JESD204B RX on DAC side.

HI NitinYadav123 

The SYNC0OUTB± signal toggling is symptomatic of the Initial Lane Synchronization (ILS) phase—that is, the link is attempting to establish itself and generate SYNC~ toggles to align code groups (CGS stage).

Common problems could include:

1. SYSREF mismatch or not properly captured for link start-up. SYSREF must align with Device Clock.
2. Lane clock/reference clock issues—unsuitable PLL/CPLL not locking.

We provide comprehensive guide—check “SYSREF captured: Yes” and “SYSREF alignment error: No”—these are key to diagnosing link states. Troubleshooting JESD204B Tx links [Analog Devices Wiki]

The UC23 test sequence must or any 204B usecase must follow the same:

• Trigger SYSREF
• Enable link state machine monitoring
• Poll status bits for CGS, ILS, IFS stages

• If IRQ or monitor registers remain zero, it may indicate the API hasn't been instructed to enable monitoring or hasn't reached the state to begin counting. Ensure the test setup follows the Reference Manual UG-1578 and JESD HDL driver recommendations. AD9081/AD9082 Software Development User Guide, UG-1578 (Rev. A)

Regards,

SJ

HI NitinYadav123 

The SYNC0OUTB± signal toggling is symptomatic of the Initial Lane Synchronization (ILS) phase—that is, the link is attempting to establish itself and generate SYNC~ toggles to align code groups (CGS stage).

Common problems could include:

1. SYSREF mismatch or not properly captured for link start-up. SYSREF must align with Device Clock.
2. Lane clock/reference clock issues—unsuitable PLL/CPLL not locking.

We provide comprehensive guide—check “SYSREF captured: Yes” and “SYSREF alignment error: No”—these are key to diagnosing link states. Troubleshooting JESD204B Tx links [Analog Devices Wiki]

The UC23 test sequence must or any 204B usecase must follow the same:

• Trigger SYSREF
• Enable link state machine monitoring
• Poll status bits for CGS, ILS, IFS stages

• If IRQ or monitor registers remain zero, it may indicate the API hasn't been instructed to enable monitoring or hasn't reached the state to begin counting. Ensure the test setup follows the Reference Manual UG-1578 and JESD HDL driver recommendations. AD9081/AD9082 Software Development User Guide, UG-1578 (Rev. A)

Regards,

SJ

Hi

Thanks for the response ! 

With the register page change we are now able to read the registers. Its show 3E on each lane that means we are getting into data phase. 

We have one more issue, on the ADC side. On JESD RX in FPGA we are getting into data phase but once we get into data phase we starts to get disparity errors. So we are not sure what could be the reason because if its due to signal integrity issue it should have come during link up also. We are using UC 8 for ADC testing, we modified this testcase to single link from dual link and also changed the resolution (N) to 16 instead of 12. I am attaching the APIs log for more reference if that could help. ad9082_app (5).log