Power consumption

Can you please let us know more details about your requirements, like the ADC/DAC sampling rate, the IBW and the JESD config parameters?

Yes, at maximum sample rate 20 GSps, iBW 10Ghz, nºADC =1, JESD204C 12 lanes at 20Gbps M=1, or an approximate case.

And for this case its possible to know the total latency. I tried to find the device in the ACE without success.

Thanks

The power consumption for a single ADC is around 11.2W depending on the configuration numbers shared by you. Are you planning to configure the chip in 1R1T mode or RX only mode?

ARRubio said:

And for this case its possible to know the total latency. I tried to find the device in the ACE without success.

Can you please share more details on the below configs:

1. Loopback mode enabled

2. CDDC and FDDC dec rate

3. Fsrc decimation

4. Programmable filter enabled

5. JESD type and JESD mode number

Only in RX mode, only 1 ADC, JESD type C at maximum speed for 20 GSPs, 12 lanes, 12 bits, no FSRC, no Filter, no Loopback

Note that 1RX only mode, is not tested by ADI. Are you keeping the CDDC bypassed to 1 and FDDC dec rate set to 1?

Then 10.9 W that you say is in 1R1T configuration, right? Nowadays, the CDDC and FDDC aren´t important, we are focus in the power consumption and latency for the best and worst case. We do not plan to use the device's DACs.

Thank you

ARRubio said:

Then 10.9 W that you say is in 1R1T configuration, right?

No, this power of around 11.2W is consumed by a single RX path. Note that this is the power consumed when the CDDC and the FDDC are kept enabled. In that case, the FDDC can accept a maximum rate of 5Gsps. So, CDDC dec factor needs to kept at 4(20/4=5Gsps). FDDC dec is kept at 1. 

If CCDC and FDDC both are kept enabled with dec of 1, then the JESD lane rate exceeds the maximum supported lane rate of 28.21Gsps. If the CDDC and FDDC are kept disabled, then though the lane rate is 20.625Gsps  and remains within the max lane rate limit, but the power consumption increases to 14.7W, as compared to 11.2W in the first case(as lesser JESD lane rate of 10.3Gsps at 5Gsps RX data rate)

Note that all these numbers are power estimate numbers, and you need to test with your use case to find out the real time numbers precisely. Also, single receive use case is not a tested use case

Under these above conditions, the maximum RX path latency is 135nsec and min RX path latency is 130nsec approx.

Then, the output data rate is limited internally to 5GSps.

But, I don´t understand when you said  "If CCDC and FDDC both are kept disabled, then the JESD lane rate exceeds the maximum supported lane rate of 28.21Gsps". There are 12 lanes at 28.1 Gbps each RX path, approximately 337 Gbps (with ideal efficiency) . The output data rate at 20 GSps at 12 b/S is 240 Gbps less than output capability. 

Thanks for all

Refer to the below maximum lane rate that is supported in JESD204C mode, 

Sorry for the confusion. Yes your understanding is correct that in disabled case, the lane rate will not exceed the max supported rate. Please see the earlier reply.