AD9081
Recommended for New Designs
The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter...
Datasheet
AD9081 on Analog.com
How does the MXFE (AD9081) handle underflow condition. Say we configure SerDes line rate at 16Gsps. But the application only requires 8Gsps. How does MXFE handle this underflow condition? Can you break down your answers for ADC path and DAC path?
Hello,
The SERDES link uses bit repeat mode such that "effective" lane rates of 8 GSPS or below can be achieved or when mismatched lane rates between two links are related by integer factor such that the PLL VCO operates at a common frequency. See description below in UG1578.
