Ad9081s synchronisation

Hi PedroKeshna 

Thank you for using AD9081.

I have moved this thread to the correct forum: Mixed-Signal Front Ends (MxFE) . Someone here should be able to support you.

Hi, it'd be appreciated if you could clarify following few points

• It sounds that there is random offset of one sample between the same ADC on different chips, correct? 
• When there is offset between two ADC, does it stay constant until the system is initialized? 
• One sample of global clock - could you clarify what is the global clock here?
• Maximum clock frequency of SPI of AD9081 is 33MHz, could you clarify how 100MHz is used as reference?
• Could you clarify how ADC clock divider power down bit is related to synchronization issue?
  • Do you expect that two ADC are synchronized if this bit on two chips are written exactly at the same time?
• The power down bit of ADC clock divider should be cleared to enable internal clock divider, to be clear.
• Are you using subclass 1? How does it behave wtih subclass 0?

There are some useful instructions on how to synchronize mutliple chips in the user guide as follows.

And also, it is mentioned in the user gude as below that deterministic latency accuracy of MCS is not possible if clock multipler D is bigger than 1, which can be configured with the register 0x0093.

Hope this is helpful and let us know if any further clarificaiton is needed.

-YH

Hi again yhkim and thanks alot for your reply.

I will answer your questions in the same order so i could clarify my problem.

1) Yes, in one chip all adcs are synchronised. But in two chips with the same index of adcs(as an example ad9081_1_adc1 and ad9081_2_adc1) They have a random 1 sample data offset with each other.

2)yes it remains constant after programming and initialization.

3)By global clk i mean the PCLK (glb clk is the name used in xilinx giga transceiver ipcores)

4)sorry the refrence clk of my spi module code is 100Mhz and the generated sclk is with a pre scaler of 4 meaning 25Mhz.

5)after a little bit of testing to find my problem i have found that in the sequence of one_shot_synchronisation if i deliberately add a delay for one chip before setting the reg 0x0180 as shown in the image below of the adi code (exp ad9081_1_adc1) and don't add any delay to the other chip's adc. it adds ups the offset between data samples of adcs and it no longer remains 1 data sample different(the randomness remains unchanged). If u do the same and add any delay before any other ragisster in the adi sequence it doesn't make any diffrence only this registers responds to the delay which shows my synchronisation is dependent on the spi timing for this register.

How ever in the sequence of the adi in the part of clock configuration ,the clock power down bit of this register is valued to 0 (meaning power up) and after the tx and rx configuration in the first stage of one shot synchronisation sequence i check agin the power down bit of this register and i surprisingly read the value of the power down bit of this register to 1(meaningpower down!!) But i'm really sure that i'm not powering down this register anywhere in my code and something else is causing this strange behaviour but any ways i power up the register in one shot sync sequence again(as show in the image above). Maybe this is why it's causing the problem? Is it normall that i'm reading the power down bit valued to 1 even that i have power it up in the clock configuration sequence befor tx and rx and one shot sync synchronisation sequences?!

6)i'm sure we are using subclass 1, and it is needed because we need deterministic latancy cause we want to achieve multiboard synchronisation at the end of project.

7)about the divider, thr pll is powerdown and we are using external clock.(5Ghz and adc clock 2.5Ghz).

I would be appreciated if u help me find and furthermore fix the problem.

Thank you for your support. Sincerely Keshna. 

Hi,

Thank you for the detailed information. Regardign the ADC clock divider, it seems that it is only enabled based on the chip revision during one shot sync configuration. I'll come back to you after I check with the team about this. In the meantime, as you are using the external clock, I'd think that you can disable the clock divider all the time. Have you tried? Or could you try to remove the code to enable clock divider and see whether there is change of behaviour? I suppose it won't affect your system, but I could be wrong.  Furthermore, the delay varies by one sample in PCLK, so the clock divider doesn't seem to be the cause.

As the difference in delay between two devices is in PCLK rather than LMFC, and also your experiement on additional delay seems to suggest that subclass 1 sync using SYSREF seems to work. If you are using single pulse SYSREF, could you chang it to periodic SYSREF and use SYSREF monitor mode to see what values you read from SYSREF_PHASE registers when two devices are aligned and when when they are off by 1 PCLK?

And also, have you verified your JESD RX IP and ruled out the possibility of 1 PCLK offset caused by JESD receiver?

We're going to look into more on this issue, and it'd be appreciated if you provide more information mentioned above.

-YH

Hi again yhkim and thank you again for your answer. I'm really appreciated.

We even tried dissabling it but it doesn't seem to be affected by this as i told the registere is powered down surprisingly some where in the process which we don't know where and furthermore we actually can't dissable the devider because we are using dacs and adc both (dac clk = 5Ghz and adc clk = 2.5 Ghz) but for just testingwe can do so. And for the statement of :

yhkim said:

Furthermore, the delay varies by one sample in PCLK, so the clock divider doesn't seem to be the cause.

I think you're wrong cause it might be setup or hold violation (which are usually less than 1 clk)and at the end shows it's self as 1 pclk difference.

We are in one shot mode but our sysrefs are continously being created by hmc7043.

We monitored the sysref_phase register and it is randomly 0 or 1 or 2 or maybe more different from lfmc but it seems it doesn'taffect the output synchronisation i mean in some tests we had phase differences between sysref and lmfc but the ouput samples where synchronised.

We can be assured that the problem is not with jesd because our start_of_frames are synchronised in all the tests and after the deserialazation of the data we get the sample differences.(I also have forgotten to mention that we are in NCO_ONLY mode) .At last thanks alot again for your support and i would be really appreciated if you help us furthermore.

Thank you for your support. Sincerely Keshna. 

Hi again yhkim  i'm here to ask one more important question.

I'm pretty sure our synchronisation problem is related to the clk devider powering on with unstablephase( as any physical divider like hmc7043 the phase will be random with out giving rfsync). In the adi i couldn't find a sequence to make sure the adc clks deviders in two chips will have synchronised power on phase. In the data sheet it is saying the adc clk devider is having a reset capability is it the power down bit or is it something else?

How to make sure two chips will have the same power on phase on their adc clks. What is the sequence for the phases to be synchronised? I would be really appreciated if you and your team help us.

Thank you for your support. Sincerely Keshna. 

Hi Keshna,

I'm still checking with the team that why it is necessary to enable the divider for certain chip revision. But the following is what I confirmed with the team.

Unlike the divider (D) that generates the DAC CLK, the the divider for ADC CLK (L) is reset by SYSREF pulse so that ADC clok may not be source of the offset.

So would it be possible to feed 2.5 GHz for both of DAC and ADC with L=1 to eliminate the possibility of offset caused by ambiguity in the phase of ADC clock?

And there are many more to consider, so it'd be helpful if you could provide more information such as,

•  SYSREF has to be DC coupled, confirm?
• Could you share details of your AD9081 sample rate and JESD configurations?
• How did you encure NCO phases are aligned?

I may come back and request more information as necessary.

-YH

Hi again yhkim and thanks again for your suport.

yhkim said:

Unlike the divider (D) that generates the DAC CLK, the the divider for ADC CLK (L) is reset by SYSREF pulse so that ADC clok may not be source of the offset.

The divider value is not the source of offset or ambiguity as you said, what I am pretty sure is "turning it on" is an async process which will be dependent to how much synchroun two SPIs are. Can you confirm that?

yhkim said:

So would it be possible to feed 2.5 GHz for both of DAC and ADC with L=1 to eliminate the possibility of offset caused by ambiguity in the phase of ADC clock?

Of coarse it is possible. I will change my setup to do so and will get back to you with result.

And to answer your three last question in order:

1) yes it is DC coupled on the PCB and is set on register 0x019A.

2)Input RF Clock: 5GHz as DAC Sample rate, L=2 so 2.5GHZ for ADC Sample Rate. IQ frequency: 625MHz (DAC DUC upsamples by 8 and ADC DDC downsamples data by 4). JESD204B, 8 Lanes, 12.5G for each lane.

3)  I am using NCO Only mode for ADCs and I confirm that my dada recieved on FPGA side are exatly the same for both devices (I mean zero diffrence). just the occasional sample shift. I'd be gratefull if you confirm I can be assured that NCOs are phase aligned doing so.

And for another test in my sequence i didn't set the clk power done bit (as it is used in the adi sequence) and i'd expected that it doesn't make any difference as it is powered down by default (datasheet default value 0x01). But surprisingly my samples shifts are not 0 or 1 now they have got larger like 7 or 8(randomness is still unchanged)!?

And one more question, is it obligatory for the sysref to be generated after the initialization of the chips or is it ok for the sysrefs to be continually generated even before the initialization of the system?

Thank you alot for your support. Sincerely Keshna. 

Hi Keshan,

Thank for the detailed information. I'll get back to you shortly.

-YH

Hi again yhkim and thank you again for your supporting and kindness.

No problem i will wait for it.

Thank you alot for your support. Sincerely Keshna.