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Working in multi-nyquist situations

Category: Software
Product Number: AD9081
Software Version: 2023_R2

Hi,
I have a project where i need to work from 100 Mhz to 7 Ghz. I am working with a device clock of 245.76Mhz in JESD204C at lane rate of 16.02216 Gbps with a sampling rate of 491.52 MSPS. The ADC sampling frequency is set to 3.93216 Ghz and DAC sampling frequency is 11.79648 Ghz.

As i would need to avoid the nyquist boundaries near the sampling rate, i would require to change the sampling frequency of the DAC/ADC based on whether the frequency is near the nyquist boundary.



My queries:

1. As i am using the ADI IIO driver to work with the AD9081, is there any way to dynamically change the sampling rate of the ADC and DAC. If so please mention the sequence and the sysfs files that i should edit.

2. Does the Driver take care of the background timing and gain calibration when approaching the nyquist boundary or is this something i have to explicitly handle.

Thread Notes

  • Hi, you cannot change the sample rate through libiio interface. To give you an idea what you can change through libiio interface, if you cannot change certain parameters on IIO OSC GUI, then you may not be able to change them through libiio interface either. Some minor changes such as reducing sample rate without changing any of JESD parameters can be made by changing the device tree, and you need to rebuild HDL beyond that.  

    I believe you need to disable background timing and gain calibration explicitly yourself if your signal falls within certain range from the boundary. I'll check and let you know otherwise.

  • I changed the sampling rate at the ADC side from 3.93216Ghz to 2.94912Ghz which meant i had to change decimation factor of 8 ( 4x - CDDC and 2x - FDDC ) to the decimation factor of 6 ( CDDC - 6x , FDDC - 1x ).

    After changing the build to 6x decimation , i was able to get the signal at expected frequencies. However i noticed that i was not able to use the ADC channelizer FDDC block components such as the 6 db gain and NCO shifter. However the CDDC / main digital path was working normally as expected.

    So i wanted to know does changing the decimation to 1x cause the FDDC to get bypassed.

  • Yes, the channerlizers are bypassed if the decimation rate is set to 1x. 

  • Since i cannot change sampling rate through IIO driver directly in the existing state, i shall plan to add a patch to take external input for the L parameter used for the ADC clock division as shown below. I am planning to add an external input sysfs file for decimation as well.

    Is it simply enough to change the division ratio at of the ADC clock ( divide by 1/2/3/4 ) or should i follow it up with some other register writes for other sections to adjust for these changes ( sampling clock and decimation ). For now i need to only change the sampling rate at the ADC side.

  • Hi, it may be possible to write some registers in theory, but that's not recommended. It'd be best to build new device tree. Could you clarify your use case? Are you trying to change the configuration on the fly? 

  • I am working in a frequency range of 100 Mhz to 7.125 Ghz. The sampling frequency i use at DAC side is 11.79648 Ghz and ADC side is 3.93216 Ghz owing to my data rate of 491.52 Mhz. As you can see, since i am using such a wide frequency range, i need to change the sampling frequency when i am near the nyquist boundary for the given sampling frequencies particularly at the ADC side where i will be going through higher number of zones compared to Tx.

    So yes i would require to change the frequency on the fly. I was assuming changing the L factor would be sufficient to achieve this along with changing the decimation correspondingly without affecting the JESD mode.

  • Thank you for the explanation. If you change the division ratio, you need to make the corresponding changes in decimation ratio as well to keep the same JESD settings, which is not always possible. Still the best way would be to modify the device driver/device tree to have multiple sets of configurations and add new IIO attribues to choose the profile you want. That's bit beyond the scope of our support, but hope this makese sense to you. 

    And the only options you have for division ratio would be to switch between 3 (fADC=3.93GHz) and 4(fADC=2.94GHz), then you need to ensure that rest of the data chain works correctly.  

    Hope this helps