Hi,
I have a project where i need to work from 100 Mhz to 7 Ghz. I am working with a device clock of 245.76Mhz in JESD204C at lane rate of 16.02216 Gbps with a sampling rate of 491.52 MSPS. The ADC sampling frequency is set to 3.93216 Ghz and DAC sampling frequency is 11.79648 Ghz.
As i would need to avoid the nyquist boundaries near the sampling rate, i would require to change the sampling frequency of the DAC/ADC based on whether the frequency is near the nyquist boundary.
My queries:
1. As i am using the ADI IIO driver to work with the AD9081, is there any way to dynamically change the sampling rate of the ADC and DAC. If so please mention the sequence and the sysfs files that i should edit.
2. Does the Driver take care of the background timing and gain calibration when approaching the nyquist boundary or is this something i have to explicitly handle.