Question

Hi, sorry for the delay. It looks that you followed the directions on the user guide correctly. FYI, the attached code is correspondign code to disable those cals with API. In future, please take a look at the API code if you are in doubt.

I am not sure whether any change is expected right after disabling the calibration. You may want to change the environemnt such as temperature, or move the tones closer to the Nyquist boundary, where you are supposed to disable some calirbations, with and without those calibration to see the effects. Please let us know if this makes sense to you.

-YH  

I tried to disable calibration using the above steps, then set the frequency close to the Nyquist boundary, and let the ADC chip run for a period of time to heat up, but I didn't see much difference in the spectrum. 

The following image was obtained by me during spectrum analysis. The red and blue colors represent the spectrum analysis before and after disabling calibration. Here, I set the sampling rate to 2G, the signal frequency to 0.98G, and the ADC heated it like bread in an oven.

Thank you for sharing the data. We'll look into it.  May I ask you why you want to disable the user calibration?

-YH

Thanks for your reply.I am using the AD9081 platform to validate my self-designed two channel correction algorithm, including offset mismatch, gain mismatch, and timing mismatch.I imported the data output by AD9081 into my computer through a network card for verification.

By the way, does the great ADI provide FPGA engineering and pre made APIs for AD9081 with a sampling rate of 4G, which can be directly imported into VCU118 for testing
I would greatly appreciate it if these could be provided, as configuring FPGA is always a headache

Thank you for the background about calibration. We'll get back to you if anything is found.

There are several example designs for VCU118 in the following page

wiki.analog.com/.../microblaze

One of the example designs for VCU118 platform in this page supports 6GHz of ADC clock in full bandwidth mode without any decimation, which results 6GSPS real stream providing 2.4 GHZ of IBW. This is for AD9082 device, and it can be modified to be used with AD9081 for 4GSPS FBW without rebuilding HDL. And there are several example designs for AD9081 providing 4GHz of ADC clock with decimation ratio of 2x1, resulting 2GSPS of complex data stream provding 1.6 GHz of IBW. With AD9081, you can get either 4GSPS real stream in FBW mode or 2 GSPS complex stream, both providing the same IBW. Please review those settings and let us know if any clarificaiton is needed.

Hope this helps

-YH