Category: Hardware
Product Number: AD9081
In our application, we are trying to change the Device clock frequency to 464MHz, and I.m using the clock input from the AD9081 board. I am starting with setting the clock frequency to 232MHz, so I can test it with the minimal change of giving HDL project. To accomplish this frequency, I set the pll2 out frequency to 2784000000, and the device clock divider = 12. Then I also change the sampling frequency for both DAC and ADC accordingly. When I tested the set up, the device clock input was locked to 232MHz correctly.
However, the JESD link was not built successfully. The same JESD204 setting works when the clk frequency is 250MHz, and I also changed the constraint file accordingly. When I checked the message during the booting session, I saw the system attempt to connect many times but failed. The final message from terminal is: "Link0 set lane rate 9280000 kHz failed (-22)"
Here are my dts file and Error report file
#include "zynq-zc706-adv7511-ad9081.dts"
&spi1 {
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <5000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
adi,pll1-ref-autorevert-enable;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll1-charge-pump-current-ua = <720>;
adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */
adi,pll2-output-frequency = <2784000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <12>; // 232
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <1536>; //
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <12>; // 232
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c10: channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <12>; // 232
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK";
adi,divider = <12>; // 232 LaneRate/40
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <1536>; //
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
};
};
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <11136000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <12>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1100000000>; /* 1100 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1200000000>; /* 1200 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1300000000>; /* 1300 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <4>;
ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
adi,link-mode = <9>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <3712000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <400000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <(-400000000)>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc3: adc@3 {
reg = <3>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan5: channel@5 {
reg = <5>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
adi,link-mode = <10>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
};
};
&fpga_axi {
axi_ad9081_rx_jesd: axi-jesd204-rx@44a90000 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x44a90000 0x1000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 1>, <&axi_ad9081_adxcvr_rx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_adxcvr_rx 0 FRAMER_LINK0_RX>;
};
axi_ad9081_tx_jesd: axi-jesd204-tx@44b90000 {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x44b90000 0x1000>;
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 1>, <&axi_ad9081_adxcvr_tx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_tx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_adxcvr_tx 0 DEFRAMER_LINK0_TX>;
};
};
Booting Linux on physical CPU 0x0
Linux version 5.10.0-98248-g1bbe32fa5182 (jenkins@romlxbuild1.adlk.analog.com) (arm-xilinx-linux-gnueabi-gcc.real (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.0.20200730) #1142 SMP PREEMPT Wed Aug 3 17:51:18 IST 2022
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Xilinx Zynq ZC706
OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found
Memory policy: Data cache writealloc
cma: Reserved 128 MiB at 0x38000000
Zone ranges:
Normal [mem 0x0000000000000000-0x000000002fffffff]
HighMem [mem 0x0000000030000000-0x000000003fffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000000000000-0x000000003fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff]
percpu: Embedded 15 pages/cpu s29900 r8192 d23348 u61440
Built 1 zonelists, mobility grouping on. Total pages: 260608
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 886152K/1048576K available (11264K kernel code, 802K rwdata, 7484K rodata, 1024K init, 347K bss, 31352K reserved, 131072K cma-reserved, 131072K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU event tracing is enabled.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x33c/0x4e0 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=25
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 32, base_baud = 3125000) is a xuartps
printk: console [ttyPS0] enabled
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
mc: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@44b60000
jesd204: created con: id=1, topo=0, link=2, /axi/spi@e0007000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44b60000 <-> /fpga-axi@0/axi-jesd204-tx@44b90000
jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44a90000
jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44b90000 <-> /fpga-axi@0/axi-ad9081-tx-hpc@44b10000
jesd204: created con: id=5, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@44a90000 <-> /fpga-axi@0/axi-ad9081-rx-hpc@44a10000
jesd204: created con: id=6, topo=0, link=2, /fpga-axi@0/axi-ad9081-rx-hpc@44a10000 <-> /axi/spi@e0006000/ad9081@0
jesd204: created con: id=7, topo=0, link=0, /fpga-axi@0/axi-ad9081-tx-hpc@44b10000 <-> /axi/spi@e0006000/ad9081@0
jesd204: /axi/spi@e0006000/ad9081@0: JESD204[0:2] transition uninitialized -> initialized
jesd204: /axi/spi@e0006000/ad9081@0: JESD204[0:0] transition uninitialized -> initialized
jesd204: found 8 devices and 1 topologies
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
nfs4filelayout_init: NFSv4 File Layout Driver Registering...
fuse: init (API version 7.32)
bounce: pool size: 64 pages
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dma-controller: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
Registered mathworks_ip class
spi-nor spi2.0: found s25fl128s1, expected n25q128a11
random: fast init done
random: crng init done
spi-nor spi2.0: trying to lock already unlocked area
spi-nor spi2.0: s25fl128s1 (32768 Kbytes)
5 fixed-partitions partitions found on MTD device spi2.0
Creating 5 MTD partitions on "spi2.0":
0x000000000000-0x000000500000 : "boot"
0x000000500000-0x000000520000 : "bootenv"
0x000000520000-0x000000540000 : "config"
0x000000540000-0x000000fc0000 : "image"
0x000000fc0000-0x000002000000 : "spare"
MACsec IEEE 802.1AE
libphy: Fixed MDIO Bus: probed
tun: Universal TUN/TAP device driver, 1.6
libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 36 (00:0a:35:00:01:22)
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver net1080
usbcore: registered new interface driver cdc_subset
usbcore: registered new interface driver zaurus
usbcore: registered new interface driver cdc_ncm
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver upd78f0730
usbserial: USB Serial support registered for upd78f0730
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
usb usb1: Manufacturer: Linux 5.10.0-98248-g1bbe32fa5182 ehci_hcd
usb usb1: SerialNumber: ci_hdrc.0
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
si570 1-005d: registered, current frequency 156250000 Hz
i2c i2c-0: Added multiplexed i2c bus 1
adv7511 2-0039: supply avdd not found, using dummy regulator
adv7511 2-0039: supply dvdd not found, using dummy regulator
adv7511 2-0039: supply pvdd not found, using dummy regulator
adv7511 2-0039: supply bgvdd not found, using dummy regulator
adv7511 2-0039: supply dvdd-3v not found, using dummy regulator
i2c i2c-0: Added multiplexed i2c bus 2
at24 3-0054: supply vcc not found, using dummy regulator
at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 3
pca953x 4-0021: supply vcc not found, using dummy regulator
pca953x 4-0021: using no AI
i2c i2c-0: Added multiplexed i2c bus 4
rtc-pcf8563 5-0051: low voltage detected, date/time is not reliable.
rtc-pcf8563 5-0051: registered as rtc0
rtc-pcf8563 5-0051: low voltage detected, date/time is not reliable.
rtc-pcf8563 5-0051: hctosys: unable to read the hardware clock
i2c i2c-0: Added multiplexed i2c bus 5
at24 6-0050: supply vcc not found, using dummy regulator
at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 6
i2c i2c-0: Added multiplexed i2c bus 7
i2c i2c-0: Added multiplexed i2c bus 8
pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
gspca_main: v2.14.0 registered
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
failed to register cpuidle driver
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
hid: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
mmc0: new high speed SDHC card at address aaaa
mmcblk0: mmc0:aaaa SC32G 29.7 GiB
mmcblk0: p1 p2 p3
hmc7044 spi1.0: PLL1: Locked, CLKIN0 @ 100000000 Hz, PFD: 1000 kHz - PLL2: Locked @ 2784.000000 MHz
jesd204: /axi/spi@e0007000/hmc7044@0,jesd204:1,parent=spi1.0: Using as SYSREF provider
axi_adxcvr 44a60000.axi-adxcvr-rx: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
axi_adxcvr 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 4.
axi_adxcvr 44b60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44B60000. Number of lanes: 4.
axi-jesd204-rx 44a90000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
axi-jesd204-tx 44b90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44B90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
axi_sysid 45000000.axi-sysid-0: [ad9081_fmca_ebz] on [zc706] git branch <hdl_2021_r1> git <b37120fba13f1102a39d08006103902dd49e5b6c> clean [2022-07-25 15:32:41] UTC
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 36
Key type dns_resolver registered
zynq_pm_remap_ocm: no compatible node found for 'xlnx,zynq-ocmc-1.0'
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
[drm] Initialized axi_hdmi_drm 1.0.0 20120930 for 70e00000.axi_hdmi on minor 0
axi-hdmi 70e00000.axi_hdmi: [drm] Cannot find any crtc or sizes
ad9081 spi0.0: supply vdd not found, using dummy regulator
ad9081 spi0.0: AD9081 Rev. 3 Grade 10 (API 1.2.2) probed
cf_axi_dds 44b10000.axi-ad9081-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x44B10000 mapped to 0x6cdaa27f, probed DDS AD9081
cf_axi_adc 44a10000.axi-ad9081-rx-hpc: ADI AIM (10.01.b) at 0x44A10000 mapped to 0xddc8f72c, probed ADC AD9081 as MASTER
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_pre_setup: Link0 set lane rate 9280000 kHz failed (-22)
jesd204: /fpga-axi@0/axi-jesd204-tx@44b90000,jesd204:5,parent=44b90000.axi-jesd204-tx: JESD204[0:0] In link_pre_setup got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_supported', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_pre_setup: Link0 set lane rate 9280000 kHz failed (-22)
jesd204: /fpga-axi@0/axi-jesd204-tx@44b90000,jesd204:5,parent=44b90000.axi-jesd204-tx: JESD204[0:0] In link_pre_setup got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_supported', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_pre_setup: Link0 set lane rate 9280000 kHz failed (-22)
jesd204: /fpga-axi@0/axi-jesd204-tx@44b90000,jesd204:5,parent=44b90000.axi-jesd204-tx: JESD204[0:0] In link_pre_setup got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_supported', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> link_supported
axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_pre_setup: Link0 set lane rate 9280000 kHz failed (-22)
jesd204: /fpga-axi@0/axi-jesd204-tx@44b90000,jesd204:5,parent=44b90000.axi-jesd204-tx: JESD204[0:0] In link_pre_setup got error from cb: -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: Rolling back from 'link_supported', got error -22
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9081@0,jesd204:0,parent=spi0.0: FSM completed with error -22
input: gpio_keys as /devices/soc0/gpio_keys/input/input0
of_cfs_init
of_cfs_init: OK
clk: Not disabling unused clocks
ALSA device list:
#0: HDMI monitor
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
systemd[1]: System time before build time, advancing clock.
systemd[1]: systemd 247.3-7+rpi1 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
systemd[1]: Detected architecture arm.
Welcome to Kuiper GNU/Linux 11.2 (bullseye)!
I went on the forum to try to find the solution to a similar problem, and I found in most case they are suggesting change the jesd pll to "QPLL1" to solve the problem. RE: Is it necessary to modify xcvr after changing jesd parameter and clock? AD9081
I checked the dts file and found it is already QPLL, then I opened the HDL project but I didn't find where to choose the QPLL type.
Could you help me to locate the p[problem and build the connection with this clock frequency?
Remove the duplicate files
[edited by: FlameF at 8:50 PM (GMT -5) on 14 Jan 2025]
