Trace widths of JESD, ADC and DAC signals are different in Evaluation Board file and the stack-up

Hi, Thank you for sharing inquiry and sharing all this information. Will check with the team and get back to you.

Hello,

RF traces on AD9081 PCB are designed and fabricated as 50 ohm or 100 ohm impedance controlled lines in fab. Line width and Spacing are adjusted for the specific impedance at the actual stack up and materials by fab company. So there are some difference at the finished actual line width and spacing to the designed ones. 

These impedance interfaces typically applies only at lower frequencies. And the parasitic on the silicon die and the package becomes dominant at the input or output impdeance at high frequency in AD9081 DAC, ADC, and Clocks operating beyond 6GHz or higher. For example, the real part of  AD9081 ADC input admittance varies from 50 ohm to 250 ohm within the 0 to 8GHz. Because of this variation in impedance vs.frequency, it is necessary to design the PCB carefully to obtain the optimum performance in the particular band of interest. Wider linewidth and spacing at ADC Input and DAC output are through the simulation to obtain the general optimum performance over a wide frequency range. And at 5 mil line and 30 mil overlay at ADC input lines, the actual line width is 30 mil, not 5 mil trace, no need that 5 mil line. We should remove this line. For the different line width and spacing at JESD SERDES line, I need to double-check but it looks like it is from the performance verified previous design.

It is suggested to refer to the eval system design file in your system design and we also provide AD9081 RF Models contained in the Keysight ADS, which can be used to design a system board. Please refer to the app note below.    

https://www.analog.com/media/en/technical-documentation/app-notes/an-2065.pdf

I hope it covers what you asked.

Thanks

Tony  

Hi Tony

Thank you for the response.

I also have a doubt regarding the trace lengths of the JESD lines and the analog signals corresponding to ADC and DAC channels.

• We have observed that the length matching is not followed for SERDES lines.
• For ADC channels, the observed trace lengths are as follows:

ADC channel 2: 2009 mils

ADC channel 0: 1509 mils

ADC channel 1: 1514 mils

ADC channel 3: 2007 mils

• For DAC channels, the observed trace lengths are as follows:      

DAC channel 0: 814 mils

DAC channel 1: 532 mils

DAC channel 2: 537 mils

DAC channel 3: 814 mils

It seems like, in ADC; Channel 0 & 1 are having almost same trace lengths and same is the case with Channel 2 & 3.

In DAC, Channels 1 & 2 have almost same trace lengths and same is the case with Channel 0 & 3.

What is the reason for this?

How are the trace lengths determined for all the above signals? What is the criterion?

Please mention the skew that has to be maintained among the ADC channels and the DAC channels.

Thank you

Hello, 

 AD9081 Eval platform was designed to check and characterize the functionality and performance of AD9081. The RF trace length difference between channels on AD9081 Eval platform was from the board layout complexity at placing all RF input/output connectors at one side where RF signals have the highest priority at PCB design. Those trace length difference and balun on the signal chain can be de-embedded with S parmater we provided in AD9081 product page. You can get S parameters of DAC and ADC models at the difference in length and use them in the ADS to simulate and analyze the performance. Please refer to application note  for this.  AN-2065: Optimizing RF Performance of the AD9081 and AD9082 | Analog Devices

The phase (timing) skew difference/mismatch on the datapath can be compensated and synched by delay adjust block and phase adjustment(in NCO) on the signal data path.  And the timing difference on JESD lanes can be aligned and synched at JESD synchronization and alignment feature/process as well. Please see UG-1578 in detail for delay and phase adjustment, and lane alignment .

However, in your own system design, it is suggested to have traces at equal length for easy compensation and adjustment. Please see "PCB Layout and Design Considerations" sections for PCB layout recommendation where it informs RF and JESD Transmission Line layout recommenations.

Thanks

THA

Thank you for the response THA.

Hi 

Can you please tell how are you shorting SGND1, SGND2 and SGNDL to the main GND_SIGNAL. In the board file, we observed isolated shapes for SGND1, SGND2 and SGNDL and couldn't find their connection to the GND_SIGNAL. 

Hi, they are connected to the common ground in the schematic (except that I couldn't find SGNDL signal). Are you saying that they are not connected to the ground in PCB file?

Yes, we found that the SGND1, SGND2, SGNDL shapes are present in layer3 but we couldn't find their connectivity to the main GND

Please find the images below

SGND1 and SGND2

SGNDL shape

Layer3

You can find the connection between SGND1,SGND2,SGND and GND on the bottom layer(see below figure). 

Please set " Edge bottom" on Color Dialogue : Display-Color-Geometry

Hi THA

Thank you for the previous response.

We have another query regarding the SERDES lines. According to the references online, we have read that 4 mils trace-width is sufficient up to 10 inches of the trace length for lower losses. The length of the SERDES lines in the Evaluation board file is around 2 to 3 inches but the trace-width and separation is 8.5 mils and 12.5 mils respectively. 

Below is the image from the reference

Reference PDF: PDF

In the AD9081-FMCA-EBZ board stack-up, for 100 ohm differential impedance, the given trace-width and separation are 4 mils and 5 mils respectively in the top and bottom layers where SERDES are routed.

We want to know what is the exact reason for routing the SERDES lines with 8.5 mils trace-width and 12.5 mil separation.

When we calculated the impedance in our tool calculator by using your stack-up, we have got 95 ohms impedance. Is the Trace-width and separation modified to reduce the impedance to 95 ohm intentionally? or is it done to minimize the losses? (because wider traces have lower losses). What impedance are you trying to target with this trace-width and length?

Kindly, help us resolve the above query.

Thank you