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Unable to work with ADC1 and ADC3 Datapath

Category: Software
Product Number: AD9081

When working with the AD9081 on my custom board, it is observed that only 2 lanes out of 4 configured for JESD data transmission seems to have valid data while rest show zeros. This data capture was observed using an ILA kept at the JESD RX within the PL section of the ZU15EG FPGA that i am working with. In addition to ILA, We also used indirect loopback to confirm the working channels ( ADC0 and ADC2 which are mapped to lanes 0 and 2 as mentioned in the dtsi attached ). To confirm that this is not an issue caused by power down of the ADCs ( RXEN based power saving ), a signal was fed through the ADC3 and routed through to the ADC0_x path using the MUX0 crossbar and looped back out through the DAC0 using indirect loopback. The data was observable in this case and a similar test case was done by routing the ADC1 through ADC0 ( Lane0 ). Both these tests ruled out the probability of the ADCs being in power down state.



The first picture on the left above shows our normal lane mapping ( Only 4 lanes are expected to be active for our current JESD configuration ). On the right is a test done to confirm whether there is a change in the lane on which data is placed. The test shows that the data is still on lane0 and lane2 on the AD9081 JESD side.

I would like to know what could be the cause for this rather weird scenario. Getting all the lanes to work is crucial in the scenario where we need all 4 ADCs to work simultaneously. Attaching the system-user.dtsi below. I am using petalinux-2022.1 and vivado 2022.1. The analog meta-adi linux kernel from github is being added as the meta-layer for the project and the 2022_R2 branch is being used.

/include/ "system-conf.dtsi"
/ {
	rx_fixed_linerate: clock@2 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16220160>;
		clock-output-names = "rx_lane_clk";
	};

	tx_fixed_linerate: clock@3 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16220160>;
		clock-output-names = "tx_lane_clk";
	};

	fixed_clk: fixed-clock {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <1179620000>;
                clock-output-names = "support_clk";
        };

	adf4377_clkin: clock@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <491520000>;
	};

	clocks {
		adf4377_12000m: clock@1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <1179648000>;	/* DAC_FREQUENCY / 10 */
			//clock-frequency =   <1179620000>;
			clock-output-names = "direct_clk_12000m";
		};
	};
};


#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>

&gem0 {
        phy-mode = "sgmii";
        is-internal-pcspma = "true";
        fixed-link {
                speed = <1000>;
                full-duplex;
         };
};

&spi1 {
        status = "okay";
        num-cs = <1>;

        hmc7044: hmc7044@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                #clock-cells = <1>;
                compatible = "adi,hmc7044";
                reg = <0>;
                spi-max-frequency = <100000>;
                jesd204-device;
                #jesd204-cells = <0x02>;
                jesd204-sysref-provider;
	       
		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
 
		adi,pll1-clkin-frequencies = <122880000 0 0 0>;

                adi,pll1-loop-bandwidth-hz = <200>;

                adi,vcxo-frequency = <122880000>;
                adi,pll1-charge-pump-current-ua = <720>;
                adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */

                adi,pll2-output-frequency = <2949120000>;

                adi,sysref-timer-divider = <1024>;
                adi,pulse-generator-mode = <0>;

                adi,clkin0-buffer-mode = <0x7>;
                adi,oscin-buffer-mode = <0x7>;

                adi,gpi-controls = <0x00 0x00 0x00 0x00>;
                adi,gpo-controls = <0x7f 0x7f 0x00 0x00>;

                clock-output-names =
                "hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
                "hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
                "hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
                "hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
                "hmc7044_out12", "hmc7044_out13";
 		hmc7044_c0: channel@0 {
                        reg = <0>;
                        adi,extended-name = "RF_PLL_C_CLK";
                        adi,divider = <6>; /*49,15,20,000 491.51MHz*/
                        adi,driver-mode = <2>;
                };
                hmc7044_c1: channel@1 {
                        reg = <1>;
                        adi,extended-name = "AD9081_C_CLK";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <2>;
			adi,jesd204-sysref-chan;
                };
                hmc7044_c2: channel@2 {
                        reg = <2>;
                        adi,extended-name = "JESD_C_GTREFCLK1";
                        adi,divider = <12>; /*49,15,20,000 491.51MHz*/
                        adi,driver-mode = <2>;
                };
                hmc7044_c3: channel@3 {
                        reg = <3>;
                        adi,extended-name = "C_FPGA_SYSREF1";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <2>;
			adi,jesd204-sysref-chan;
                };
                hmc7044_c4: channel@4 {
                        reg = <4>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
/*
                        adi,extended-name = "JESD_C_GTREFCLK2";
                        adi,divider = <12>; 
                        adi,driver-mode = <2>;
*/
                };
                hmc7044_c5: channel@5 {
                        reg = <5>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;

/*
                        adi,extended-name = "C_FPGA_SYSREF2";
                        adi,divider = <1536>;
                        adi,driver-mode = <2>;
			adi,jesd204-sysref-chan;
*/
                };
 		hmc7044_c6: channel@6 {
                        reg = <6>;
                        adi,extended-name = "JESD_C_DEVCLK1";
                        adi,divider = <12>;   /*24,57,60,000 245.76MHz dont forget to change back to 6*/
                        adi,driver-mode = <2>;
                };
                hmc7044_c7: channel@7 {
                        reg = <7>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
			adi,jesd204-sysref-chan;
                };
                hmc7044_c8: channel@8 {
                        reg = <8>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;

/*
                        adi,extended-name = "JESD_C_DEVCLK2";
                        adi,divider = <12>;
                        adi,driver-mode = <2>;
*/
                };
                hmc7044_c9: channel@9 {
                        reg = <9>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
			adi,jesd204-sysref-chan;
                };
                hmc7044_c10: channel@10 {
                        reg = <10>;
		/*
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; 
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
		*/

                        adi,extended-name = "RSVD_C_CLK_1";
                        adi,divider = <12>; 
                        adi,driver-mode = <2>;
                };
 		hmc7044_c11: channel@11 {
                        reg = <11>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
			adi,jesd204-sysref-chan;
                };
                hmc7044_c12: channel@12 {
                        reg = <12>;
                        adi,extended-name = "UNUSED";
                        adi,divider = <1536>; /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;

/*
                        adi,extended-name = "DBG_C_CLK";
                        adi,divider = <12>;
                        adi,driver-mode = <2>;
*/
                };
                hmc7044_c13: channel@13 {
                        reg = <13>;
                        adi,extended-name = "DEV_CLK_DUP";
                        adi,divider = <1536>;  /*19,20,000 1.92MHz*/
                        adi,driver-mode = <0>;
                        adi,startup-mode-dynamic-enable;
                        adi,driver-impedance-mode = <1>;
			adi,jesd204-sysref-chan;
                };
        };
};

&jesd204c_axi_ad9081_rx_adc_tpl_core {
			compatible = "adi,axi-ad9081-rx-1.0";
			reg = <0x0 0x80040000 0x0 0x10000>;

/*			dmas = <&rx_dma 0>;
			dma-names = "rx";
*/
			spibus-connected = <&trx0_ad9081>;

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&jesd204c_rx_axi 0 FRAMER_LINK0_RX>;
};

&jesd204c_axi_ad9081_tx_dac_tpl_core {
			compatible = "adi,axi-ad9081-tx-1.0";
			reg = <0x0 0x80050000 0x0 0x10000>;
/*
			dmas = <&tx_dma 0>;
			dma-names = "tx";
*/
			clocks = <&trx0_ad9081 1>;
			clock-names = "sampl_clk";
			spibus-connected = <&trx0_ad9081>;
/*
			//adi,axi-pl-fifo-enable;
			adi,axi-data-offload-connected = <&axi_data_offload_tx>;
*/
			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&jesd204c_tx_axi 0 DEFRAMER_LINK0_TX>;
};



&jesd204c_rx_axi {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0x0 0x80010000 0x0 0x10000>;

			interrupts = <0 90 4>;

			clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&rx_fixed_linerate 0>;
			clock-names = "s_axi_aclk", "device_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
};


&jesd204c_tx_axi {
			compatible = "adi,axi-jesd204-tx-1.0";
			reg = <0x0 0x80020000 0x0 0x10000>;

			interrupts = <0 89 4>;

			clocks = <&zynqmp_clk 71>, <&hmc7044 6>,  <&tx_fixed_linerate 0>;
			clock-names = "s_axi_aclk", "device_clk", "lane_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_tx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;
};



&spi0 {
        is-decoded-cs = <0>;
        num-cs = <2>;
        status = "okay";
 
    trx0_ad9081:ad9081@0 {

		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "adi,ad9081";
		reg = <0>;
		spi-max-frequency = <5000000>;


		//clocks = <&fixed_clk 0>;
		//clock-names = "support_clk";

//		clocks = <&hmc7044 0>;
//              clock-names = "dev_clk";
	
	        //clocks = <&adf4377>;
                //clock-names = "dev_clk";		
//	
		clocks = <&adf4377_12000m>;	/* dev_clk 11796480000Hz */
		dev_clk-clock-scales = <1 10>;
		clock-names = "dev_clk";

		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		jesd204-device;
		#jesd204-cells = <2>;
		jesd204-top-device = <0>; /* This is the TOP device */
		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
		jesd204-ignore-errors;//TODO DEBUG ONLY REMOVE LATER

		jesd204-inputs =
			<&jesd204c_axi_ad9081_rx_adc_tpl_core 0 FRAMER_LINK0_RX>,
			<&jesd204c_axi_ad9081_tx_dac_tpl_core 0 DEFRAMER_LINK0_TX>;

		adi,tx-dacs {
			#size-cells = <0>;
			#address-cells = <1>;

			adi,dac-frequency-hz = /bits/ 64 <11796480000>;

			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;

				adi,interpolation = <6>;

				ad9081_dac0: dac@0 {
					reg = <0>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
				};
				ad9081_dac1: dac@1 {
					reg = <1>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
				};
				ad9081_dac2: dac@2 {
					reg = <2>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
				};
				ad9081_dac3: dac@3 {
					reg = <3>;
					adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
				};

			};
			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;
				adi,interpolation = <4>;

				ad9081_tx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_tx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_tx_fddc_chan2: channel@2 {
					reg = <2>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_tx_fddc_chan3: channel@3 {
					reg = <3>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_tx_jesd_l0: link@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;

					adi,link-mode = <9>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */

					adi,converters-per-device = <8>;	/* JESD M */
					adi,octets-per-frame = <4>;		/* JESD F */

					adi,frames-per-multiframe = <64>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <4>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <0>;			/* JESD HD */

					adi,tpl-phase-adjust = <0x3>;
				};
			};
		};

		adi,rx-adcs {
			#size-cells = <0>;
			#address-cells = <1>;

			adi,adc-frequency-hz = /bits/ 64 <3932160000>;
                                                     
			adi,main-data-paths {
				#address-cells = <1>;
				#size-cells = <0>;


				ad9081_adc0: adc@0 {
					reg = <0>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
					//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
				};
				ad9081_adc1: adc@1 {
					reg = <1>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <(100000000)>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
					//adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
				};
				ad9081_adc2: adc@2 {
					reg = <2>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
					//adi,crossbar-select = <&ad9081_rx_fddc_chan4>, <&ad9081_rx_fddc_chan6>; /* Static for now */
				};
				ad9081_adc3: adc@3 {
					reg = <3>;
					adi,decimation = <4>;
					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
					//adi,crossbar-select = <&ad9081_rx_fddc_chan5>, <&ad9081_rx_fddc_chan7>; /* Static for now */
				};
			};

			adi,channelizer-paths {
				#address-cells = <1>;
				#size-cells = <0>;


				ad9081_rx_fddc_chan0: channel@0 {
					reg = <0>;
					adi,decimation = <2>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_rx_fddc_chan1: channel@1 {
					reg = <1>;
					adi,decimation = <2>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_rx_fddc_chan4: channel@4 {
					reg = <4>;
					adi,decimation = <2>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
				ad9081_rx_fddc_chan5: channel@5 {
					reg = <5>;
					adi,decimation = <2>;
					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

				};
			};

			adi,jesd-links {
				#size-cells = <0>;
				#address-cells = <1>;

				ad9081_rx_jesd_l0: link@0 {
					reg = <0>;
					adi,converter-select =
						<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
						<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
						<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
						<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;

					adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;

					adi,link-mode = <10>;			/* JESD Quick Configuration Mode */
					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
					adi,dual-link = <0>;			/* JESD Dual Link Mode */

					adi,converters-per-device = <8>;	/* JESD M */
					adi,octets-per-frame = <4>;		/* JESD F */

					adi,frames-per-multiframe = <64>;	/* JESD K */
					adi,converter-resolution = <16>;	/* JESD N */
					adi,bits-per-sample = <16>;		/* JESD NP' */
					adi,control-bits-per-sample = <0>;	/* JESD CS */
					adi,lanes-per-device = <4>;		/* JESD L */
					adi,samples-per-converter-per-frame = <1>; /* JESD S */
					adi,high-density = <0>;			/* JESD HD */
				};
			};
		};
	};
       spidev@1 {
                compatible = "lwn,bk4";
                reg = <1>;
                status = "okay";
                spi-max-frequency = <10000000>;
        };
};




lane number correction
[edited by: AflahAfu at 6:25 PM (GMT -5) on 22 Nov 2024]

Thread Notes

Parents
  • Hi, Recently we were able to configure the Ramp signal test mode on the ADC and loop it back to the DAC. An ILA capture image is added below showing data on all 4 lanes. This means that there is some mapping issue for the CDDC and FDDC assigned to RX1 and RX3 which is resulting in the traffic not reaching the lanes. An additional 2nd snippet is also attached showing the normal case where no data is present in lanes 1 and 3.






  • Sorry for the delay. You may want to try hdl_2023_r2 as meta-adi for 2023.2 is also available now. We plan to have the similar set up in our lab sometime next week and will examin whether the same issue is observed.

  • Apologies for the incorrect mapping i mentioned and have edited the same in my replies to avoid confusion for anybody following this discussion. I will try with the alternative 2,3,6,7 once i get my hands on the hardware.

  • As a part of the debugging of this ADC issue, i tried to run the single MXFE in the same JESD204c configuration that i am running on the custom board. As a part of this testing, i am facing some issues that i have raised as another query in engineer zone. Could you please help there as well.

    https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/591387/jesd-fsm-completion

  • Hi yhkim,

    I have been successfully able to configure the AD9081 single MXFE eval board to work in the same configuration as my custom board ( JESD204C at 16.22016 Gbps ).

    https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/591387/jesd-fsm-completion

    However, i am not able to replicate the odd lane issue on the single MXFE. All the lanes are showing noise data when the ILA kept at the RX JESD of the ZCU102 is inspected which was not the case in my custom board.

    I have yet to send data and check loopback at FPGA end through all the ADCs to confirm completely. Anyway this observation is very confusing as currently the testing environment in terms of design is identical.

  • I have confirmed that all the four channels on the AD9081 single MXFE is working with the custom board jesd204C dtsi in loopback mode. This result is giving me headaches since now there is almost nothing in my mind that can differentiate the two setups. ( same driver, same git branch, same dtsi, same FDDC-CDDC mapping ).

    What logical reason is there for the device to show to different behaviours for lane 1 and lane 3 in the two setups with the same configurations.

    Let me summarize the results from the beginning of the discussion till now. Initially our issue began when we noticed that there were no data on ADC1 and ADC3 ( FDDC 0, 1, 4, 5 were used ). Thereafter we tried a different FDDC combination ( FDDC 0, 2, 4, 6 ) which resulted in data being observable at the ADC1 and ADC3. However it was noticed later that the CDDC NCO shifting was not properly happening and only the frequency that was initially set in the device tree was getting reflected properly. To validate this on the Single mxfe, the JESD204C was brought up on the eval board with the zcu102 setup and we observed none of the mentioned issues on the single mxfe. so why is the single mxfe perfectly working whereas the custom board is not under the same software environment.

    meta-adi user layer branch used is 2023_R2 under github.

  • I believe the problem is that the CDDC-FDDC mapping is hard wired in the device driver so that your intended mapping (FDDC0, 2, 4, 6) doesn't work. I'm not suprised if it works in loopback mode. So I'm confused about what you are trying to verify. And also it is not clear to me what was cuased by "CDDC NCO shifting was not properly happening". Clarification would be appreciated.

  • Sorry if i have induced confusion. I shall mention the tests done that are to be noted in this discussion:

    The first dts below shows the device tree used on the custom board with FDDC 0 1 4 5. In this case our custom board showed data on RX JESD ILA as well as FPGA loopback for ADC0 ( lane0 - FDDC0) and ADC2 ( lane2 - FDDC4 ). Note even AD9081 indirect loopback is not working for ADC1 and ADC3

    Custom board dts

    /include/ "system-conf.dtsi"
    / {
    	rx_fixed_linerate: clock@2 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <16220160>;
    		clock-output-names = "rx_lane_clk";
    	};
    
    	tx_fixed_linerate: clock@3 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <16220160>;
    		clock-output-names = "tx_lane_clk";
    	};
    
    	fixed_clk: fixed-clock {
                    compatible = "fixed-clock";
                    #clock-cells = <0>;
                    clock-frequency = <1179620000>;
                    clock-output-names = "support_clk";
            };
    
    	adf4377_clkin: clock@0 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <491520000>;
    	};
    
    	clocks {
    		adf4377_12000m: clock@1 {
    			#clock-cells = <0>;
    			compatible = "fixed-clock";
    			clock-frequency = <1179648000>;	/* DAC_FREQUENCY / 10 */
    			//clock-frequency =   <1179620000>;
    			clock-output-names = "direct_clk_12000m";
    		};
    	};
    };
    
    
    #include <dt-bindings/iio/frequency/hmc7044.h>
    #include <dt-bindings/iio/adc/adi,ad9081.h>
    
    &gem0 {
            phy-mode = "sgmii";
            is-internal-pcspma = "true";
            fixed-link {
                    speed = <1000>;
                    full-duplex;
             };
    };
    
    &spi1 {
            status = "okay";
            num-cs = <1>;
    
            hmc7044: hmc7044@0 {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    #clock-cells = <1>;
                    compatible = "adi,hmc7044";
                    reg = <0>;
                    spi-max-frequency = <100000>;
                    jesd204-device;
                    #jesd204-cells = <0x02>;
                    jesd204-sysref-provider;
    	       
    		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
     
    		adi,pll1-clkin-frequencies = <122880000 0 0 0>;
    
                    adi,pll1-loop-bandwidth-hz = <200>;
    
                    adi,vcxo-frequency = <122880000>;
                    adi,pll1-charge-pump-current-ua = <720>;
                    adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */
    
                    adi,pll2-output-frequency = <2949120000>;
    
                    adi,sysref-timer-divider = <1024>;
                    adi,pulse-generator-mode = <0>;
    
                    adi,clkin0-buffer-mode = <0x7>;
                    adi,oscin-buffer-mode = <0x7>;
    
                    adi,gpi-controls = <0x00 0x00 0x00 0x00>;
                    adi,gpo-controls = <0x7f 0x7f 0x00 0x00>;
    
                    clock-output-names =
                    "hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
                    "hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
                    "hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
                    "hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
                    "hmc7044_out12", "hmc7044_out13";
     		hmc7044_c0: channel@0 {
                            reg = <0>;
                            adi,extended-name = "RF_PLL_C_CLK";
                            adi,divider = <6>; /*49,15,20,000 491.51MHz*/
                            adi,driver-mode = <2>;
                    };
                    hmc7044_c1: channel@1 {
                            reg = <1>;
                            adi,extended-name = "AD9081_C_CLK";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <2>;
    			adi,jesd204-sysref-chan;
                    };
                    hmc7044_c2: channel@2 {
                            reg = <2>;
                            adi,extended-name = "JESD_C_GTREFCLK1";
                            adi,divider = <12>; /*49,15,20,000 491.51MHz*/
                            adi,driver-mode = <2>;
                    };
                    hmc7044_c3: channel@3 {
                            reg = <3>;
                            adi,extended-name = "C_FPGA_SYSREF1";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <2>;
    			adi,jesd204-sysref-chan;
                    };
                    hmc7044_c4: channel@4 {
                            reg = <4>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    /*
                            adi,extended-name = "JESD_C_GTREFCLK2";
                            adi,divider = <12>; 
                            adi,driver-mode = <2>;
    */
                    };
                    hmc7044_c5: channel@5 {
                            reg = <5>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    
    /*
                            adi,extended-name = "C_FPGA_SYSREF2";
                            adi,divider = <1536>;
                            adi,driver-mode = <2>;
    			adi,jesd204-sysref-chan;
    */
                    };
     		hmc7044_c6: channel@6 {
                            reg = <6>;
                            adi,extended-name = "JESD_C_DEVCLK1";
                            adi,divider = <12>;   /*24,57,60,000 245.76MHz dont forget to change back to 6*/
                            adi,driver-mode = <2>;
                    };
                    hmc7044_c7: channel@7 {
                            reg = <7>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    			adi,jesd204-sysref-chan;
                    };
                    hmc7044_c8: channel@8 {
                            reg = <8>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    
    /*
                            adi,extended-name = "JESD_C_DEVCLK2";
                            adi,divider = <12>;
                            adi,driver-mode = <2>;
    */
                    };
                    hmc7044_c9: channel@9 {
                            reg = <9>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    			adi,jesd204-sysref-chan;
                    };
                    hmc7044_c10: channel@10 {
                            reg = <10>;
    		/*
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; 
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    		*/
    
                            adi,extended-name = "RSVD_C_CLK_1";
                            adi,divider = <12>; 
                            adi,driver-mode = <2>;
                    };
     		hmc7044_c11: channel@11 {
                            reg = <11>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    			adi,jesd204-sysref-chan;
                    };
                    hmc7044_c12: channel@12 {
                            reg = <12>;
                            adi,extended-name = "UNUSED";
                            adi,divider = <1536>; /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    
    /*
                            adi,extended-name = "DBG_C_CLK";
                            adi,divider = <12>;
                            adi,driver-mode = <2>;
    */
                    };
                    hmc7044_c13: channel@13 {
                            reg = <13>;
                            adi,extended-name = "DEV_CLK_DUP";
                            adi,divider = <1536>;  /*19,20,000 1.92MHz*/
                            adi,driver-mode = <0>;
                            adi,startup-mode-dynamic-enable;
                            adi,driver-impedance-mode = <1>;
    			adi,jesd204-sysref-chan;
                    };
            };
    };
    
    &jesd204c_axi_ad9081_rx_adc_tpl_core {
    			compatible = "adi,axi-ad9081-rx-1.0";
    			reg = <0x0 0x80040000 0x0 0x10000>;
    
    /*			dmas = <&rx_dma 0>;
    			dma-names = "rx";
    */
    			spibus-connected = <&trx0_ad9081>;
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&jesd204c_rx_axi 0 FRAMER_LINK0_RX>;
    };
    
    &jesd204c_axi_ad9081_tx_dac_tpl_core {
    			compatible = "adi,axi-ad9081-tx-1.0";
    			reg = <0x0 0x80050000 0x0 0x10000>;
    /*
    			dmas = <&tx_dma 0>;
    			dma-names = "tx";
    */
    			clocks = <&trx0_ad9081 1>;
    			clock-names = "sampl_clk";
    			spibus-connected = <&trx0_ad9081>;
    /*
    			//adi,axi-pl-fifo-enable;
    			adi,axi-data-offload-connected = <&axi_data_offload_tx>;
    */
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&jesd204c_tx_axi 0 DEFRAMER_LINK0_TX>;
    };
    
    
    
    &jesd204c_rx_axi {
    			compatible = "adi,axi-jesd204-rx-1.0";
    			reg = <0x0 0x80010000 0x0 0x10000>;
    
    			interrupts = <0 90 4>;
    
    			clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&rx_fixed_linerate 0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    			#clock-cells = <0>;
    			clock-output-names = "jesd_rx_lane_clk";
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
    };
    
    
    &jesd204c_tx_axi {
    			compatible = "adi,axi-jesd204-tx-1.0";
    			reg = <0x0 0x80020000 0x0 0x10000>;
    
    			interrupts = <0 89 4>;
    
    			clocks = <&zynqmp_clk 71>, <&hmc7044 6>,  <&tx_fixed_linerate 0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    			#clock-cells = <0>;
    			clock-output-names = "jesd_tx_lane_clk";
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;
    };
    
    
    
    &spi0 {
            is-decoded-cs = <0>;
            num-cs = <2>;
            status = "okay";
     
        trx0_ad9081:ad9081@0 {
    
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,ad9081";
    		reg = <0>;
    		spi-max-frequency = <5000000>;
    
    
    		//clocks = <&fixed_clk 0>;
    		//clock-names = "support_clk";
    
    //		clocks = <&hmc7044 0>;
    //              clock-names = "dev_clk";
    	
    	        //clocks = <&adf4377>;
                    //clock-names = "dev_clk";		
    //	
    		clocks = <&adf4377_12000m>;	/* dev_clk 11796480000Hz */
    		dev_clk-clock-scales = <1 10>;
    		clock-names = "dev_clk";
    
    		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
    		#clock-cells = <1>;
    
    		jesd204-device;
    		#jesd204-cells = <2>;
    		jesd204-top-device = <0>; /* This is the TOP device */
    		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
    		jesd204-ignore-errors;//TODO DEBUG ONLY REMOVE LATER
    
    		jesd204-inputs =
    			<&jesd204c_axi_ad9081_rx_adc_tpl_core 0 FRAMER_LINK0_RX>,
    			<&jesd204c_axi_ad9081_tx_dac_tpl_core 0 DEFRAMER_LINK0_TX>;
    
    		adi,tx-dacs {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			adi,dac-frequency-hz = /bits/ 64 <11796480000>;
    
    			adi,main-data-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    				adi,interpolation = <6>;
    
    				ad9081_dac0: dac@0 {
    					reg = <0>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac1: dac@1 {
    					reg = <1>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac2: dac@2 {
    					reg = <2>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac3: dac@3 {
    					reg = <3>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    
    			};
    			adi,channelizer-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				adi,interpolation = <4>;
    
    				ad9081_tx_fddc_chan0: channel@0 {
    					reg = <0>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan1: channel@1 {
    					reg = <1>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan2: channel@2 {
    					reg = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan3: channel@3 {
    					reg = <3>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    			};
    
    			adi,jesd-links {
    				#size-cells = <0>;
    				#address-cells = <1>;
    
    				ad9081_tx_jesd_l0: link@0 {
    					#address-cells = <1>;
    					#size-cells = <0>;
    					reg = <0>;
    
    					adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    
    					adi,link-mode = <9>;			/* JESD Quick Configuration Mode */
    					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
    					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    					adi,dual-link = <0>;			/* JESD Dual Link Mode */
    
    					adi,converters-per-device = <8>;	/* JESD M */
    					adi,octets-per-frame = <4>;		/* JESD F */
    
    					adi,frames-per-multiframe = <64>;	/* JESD K */
    					adi,converter-resolution = <16>;	/* JESD N */
    					adi,bits-per-sample = <16>;		/* JESD NP' */
    					adi,control-bits-per-sample = <0>;	/* JESD CS */
    					adi,lanes-per-device = <4>;		/* JESD L */
    					adi,samples-per-converter-per-frame = <1>; /* JESD S */
    					adi,high-density = <0>;			/* JESD HD */
    
    					adi,tpl-phase-adjust = <0x3>;
    				};
    			};
    		};
    
    		adi,rx-adcs {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			adi,adc-frequency-hz = /bits/ 64 <3932160000>;
                                                         
    			adi,main-data-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    
    				ad9081_adc0: adc@0 {
    					reg = <0>;
    					adi,decimation = <4>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
    				};
    				ad9081_adc1: adc@1 {
    					reg = <1>;
    					adi,decimation = <4>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <(100000000)>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					//adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
    				};
    				ad9081_adc2: adc@2 {
    					reg = <2>;
    					adi,decimation = <4>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					//adi,crossbar-select = <&ad9081_rx_fddc_chan4>, <&ad9081_rx_fddc_chan6>; /* Static for now */
    				};
    				ad9081_adc3: adc@3 {
    					reg = <3>;
    					adi,decimation = <4>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <100000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					//adi,crossbar-select = <&ad9081_rx_fddc_chan5>, <&ad9081_rx_fddc_chan7>; /* Static for now */
    				};
    			};
    
    			adi,channelizer-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    
    				ad9081_rx_fddc_chan0: channel@0 {
    					reg = <0>;
    					adi,decimation = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan1: channel@1 {
    					reg = <1>;
    					adi,decimation = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan4: channel@4 {
    					reg = <4>;
    					adi,decimation = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan5: channel@5 {
    					reg = <5>;
    					adi,decimation = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    			};
    
    			adi,jesd-links {
    				#size-cells = <0>;
    				#address-cells = <1>;
    
    				ad9081_rx_jesd_l0: link@0 {
    					reg = <0>;
    					adi,converter-select =
    						<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
    						<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
    						<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
    						<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
    
    					adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
    
    					adi,link-mode = <10>;			/* JESD Quick Configuration Mode */
    					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
    					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    					adi,dual-link = <0>;			/* JESD Dual Link Mode */
    
    					adi,converters-per-device = <8>;	/* JESD M */
    					adi,octets-per-frame = <4>;		/* JESD F */
    
    					adi,frames-per-multiframe = <64>;	/* JESD K */
    					adi,converter-resolution = <16>;	/* JESD N */
    					adi,bits-per-sample = <16>;		/* JESD NP' */
    					adi,control-bits-per-sample = <0>;	/* JESD CS */
    					adi,lanes-per-device = <4>;		/* JESD L */
    					adi,samples-per-converter-per-frame = <1>; /* JESD S */
    					adi,high-density = <0>;			/* JESD HD */
    				};
    			};
    		};
    	};
           spidev@1 {
                    compatible = "lwn,bk4";
                    reg = <1>;
                    status = "okay";
                    spi-max-frequency = <10000000>;
            };
    };



    The second dts below shows the device tree used on the single MXFE with FDDC 0 1 4 5. In this case the single MXFE is working fine and data is present on all 4 Rx JESDs when observing the ILA as well as the loopbacks ( indirect and FPGA loopback ).

    single mxfe dts

    /include/ "system-conf.dtsi"
    / {
            rx_fixed_linerate: clock@2 {
                    #clock-cells = <0>;
                    compatible = "fixed-clock";
                    clock-frequency = <16220160>;
                    clock-output-names = "rx_lane_clk";
            };
    
            tx_fixed_linerate: clock@3 {
                    #clock-cells = <0>;
                    compatible = "fixed-clock";
                    clock-frequency = <16220160>;
                    clock-output-names = "tx_lane_clk";
            };
    
    	ref_clk_0: ref_clk_0 {
    		#clock-cells = <0>;
    		clock-frequency = <245760000>;
    		compatible = "fixed-clock";
    	};
    };
    
    #include <dt-bindings/iio/frequency/hmc7044.h>
    #include <dt-bindings/iio/adc/adi,ad9081.h>
    
    &spi1 {
    	status = "okay";
    
    	hmc7044: hmc7044@0 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		#clock-cells = <1>;
    		compatible = "adi,hmc7044";
    		reg = <0>;
    		spi-max-frequency = <1000000>;
    
    		jesd204-device;
    		#jesd204-cells = <2>;
    		jesd204-sysref-provider;
    
    //		adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
    
    		/*
    		* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
    		* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
    		* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
    		* To determine which board is which, read the freqency printed on the VCXO
    		* or use the fru-dump utility:
    		* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
    		*/
    
    		//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
    		//adi,vcxo-frequency = <122880000>;
    
    		adi,clkin1-vco-in-enable;
    		adi,pll1-clkin-frequencies = <100000000 2949120000 0 0>;
    //		adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */
    //		adi,pll1-ref-autorevert-enable;
    		adi,vcxo-frequency = <100000000>;
    
    //		adi,pll1-loop-bandwidth-hz = <200>;
    //		adi,pll1-charge-pump-current-ua = <720>;
    //		adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */
    
    		adi,pll2-output-frequency = <3000000000>;
    
    //		adi,sysref-timer-divider = <1024>;
    //		adi,pulse-generator-mode = <0>;
    
    		adi,clkin0-buffer-mode  = <0x07>;
    		adi,clkin1-buffer-mode  = <0x07>;
    		adi,oscin-buffer-mode = <0x15>;
    
    		adi,gpi-controls = <0x00 0x00 0x00 0x00>;
    		adi,gpo-controls = <0x37 0x33 0x00 0x00>;
    
    		clock-output-names =
    		"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
    		"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
    		"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
    		"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
    		"hmc7044_out12", "hmc7044_out13";
    
    		hmc7044_c0: channel@0 {
    			reg = <0>;
    			adi,extended-name = "CORE_CLK_RX";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    
    		};
    		hmc7044_c2: channel@2 {
    			reg = <2>;
    			adi,extended-name = "DEV_REFCLK";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    		};
    		hmc7044_c3: channel@3 {
    			reg = <3>;
    			adi,extended-name = "DEV_SYSREF";
    			adi,divider = <1536>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    			adi,jesd204-sysref-chan;
    		};
    
    		hmc7044_c6: channel@6 {
    			reg = <6>;
    			adi,extended-name = "CORE_CLK_TX";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    		};
    
    		hmc7044_c8: channel@8 {
    			reg = <8>;
    			adi,extended-name = "FPGA_REFCLK1";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    		};
    		hmc7044_c10: channel@10 {
    			reg = <10>;
    			adi,extended-name = "CORE_CLK_RX_ALT";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    		};
    
    		hmc7044_c12: channel@12 {
    			reg = <12>;
    			adi,extended-name = "FPGA_REFCLK2";
    			adi,divider = <12>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    		};
    		hmc7044_c13: channel@13 {
    			reg = <13>;
    			adi,extended-name = "FPGA_SYSREF";
    			adi,divider = <1536>;
    			adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
    			adi,jesd204-sysref-chan;
    		};
    	};
    };
    
    /*
    &misc_clk_0 {
    			#clock-cells = <0>;
    			clock-frequency = <245760000>;
    			compatible = "fixed-clock";
    };
    */
    &JESD_INTERFACE_axi_mxfe_rx_jesd_adc_tpl_core {
    			compatible = "adi,axi-ad9081-rx-1.0";
    			reg = <0x0 0x84a10000 0x0 0x2000>;
    //			dmas = <&axi_mxfe_rx_dma 0>;
    //			dma-names = "rx";
    			spibus-connected = <&trx0_ad9081>;
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&JESD_INTERFACE_axi_mxfe_rx_jesd_rx_axi 0 FRAMER_LINK0_RX>;
    		};
    
    &JESD_INTERFACE_axi_mxfe_tx_jesd_dac_tpl_core {
    			compatible = "adi,axi-ad9081-tx-1.0";
    			reg = <0x0 0x84b10000 0x0 0x4000>;
    //			dmas = <&axi_mxfe_tx_dma 0>;
    //			dma-names = "tx";
    			clocks = <&trx0_ad9081 1>;
    			clock-names = "sampl_clk";
    			spibus-connected = <&trx0_ad9081>;
    			//adi,axi-pl-fifo-enable;
    //			adi,axi-data-offload-connected = <&mxfe_tx_data_offload_i_data_offload>;
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&JESD_INTERFACE_axi_mxfe_tx_jesd_tx_axi 0 DEFRAMER_LINK0_TX>;
    		};
    
    &JESD_INTERFACE_axi_mxfe_rx_jesd_rx_axi {
    			compatible = "adi,axi-jesd204-rx-1.0";
                            interrupts = <0 107 4>;
                            reg = <0x0 0x84a90000 0x0 0x4000>;
    
    			clocks = <&zynqmp_clk 71>, <&hmc7044 0>, <&rx_fixed_linerate 0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    			#clock-cells = <0>;
    			clock-output-names = "jesd_rx_lane_clk";
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
    		};
    
    &JESD_INTERFACE_axi_mxfe_tx_jesd_tx_axi {
    			compatible = "adi,axi-jesd204-tx-1.0";
                            interrupts = <0 106 4>;
                            reg = <0x0 0x84b90000 0x0 0x4000>;
    
    			clocks = <&zynqmp_clk 71>, <&hmc7044 0>, <&tx_fixed_linerate 0>;
    			clock-names = "s_axi_aclk", "device_clk", "lane_clk";
    
    			#clock-cells = <0>;
    			clock-output-names = "jesd_tx_lane_clk";
    
    			jesd204-device;
    			#jesd204-cells = <2>;
    			jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;
    		};
    
    &spi0 {
            is-decoded-cs = <0>;
            num-cs = <2>;
            status = "okay";
    
    	trx0_ad9081: ad9081@0 {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		compatible = "adi,ad9081";
    		reg = <0>;
    		spi-max-frequency = <5000000>;
    
    		/* Clocks */
    		clocks = <&hmc7044 2>;
    		clock-names = "dev_clk";
    
    		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
    		#clock-cells = <1>;
    
    
    		reset-gpios = <&gpio 133 0>;
    		sysref-req-gpios = <&gpio 121 0>;
    		rx2-enable-gpios = <&gpio 135 0>;
    		rx1-enable-gpios = <&gpio 134 0>;
    		tx2-enable-gpios = <&gpio 137 0>;
    		tx1-enable-gpios = <&gpio 136 0>;
    
    		jesd204-device;
    		#jesd204-cells = <2>;
    		jesd204-top-device = <0>; /* This is the TOP device */
    		jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
    		jesd204-ignore-errors;
    
    		jesd204-inputs =
    			<&JESD_INTERFACE_axi_mxfe_rx_jesd_adc_tpl_core 0 FRAMER_LINK0_RX>,
    			<&JESD_INTERFACE_axi_mxfe_tx_jesd_dac_tpl_core 0 DEFRAMER_LINK0_TX>;
    
    		adi,tx-dacs {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			adi,dac-frequency-hz = /bits/ 64 <11796480000>;
    
    			adi,main-data-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    				adi,interpolation = <6>;
    
    				ad9081_dac0: dac@0 {
    					reg = <0>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac1: dac@1 {
    					reg = <1>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac2: dac@2 {
    					reg = <2>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    				ad9081_dac3: dac@3 {
    					reg = <3>;
    					adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
    					adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
    				};
    
    			};
    			adi,channelizer-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    				adi,interpolation = <4>;
    
    				ad9081_tx_fddc_chan0: channel@0 {
    					reg = <0>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan1: channel@1 {
    					reg = <1>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan2: channel@2 {
    					reg = <2>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_tx_fddc_chan3: channel@3 {
    					reg = <3>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    			};
    
    			adi,jesd-links {
    				#size-cells = <0>;
    				#address-cells = <1>;
    
    				ad9081_tx_jesd_l0: link@0 {
    					#address-cells = <1>;
    					#size-cells = <0>;
    					reg = <0>;
    
    					adi,logical-lane-mapping = /bits/ 8 <0 2 7 7 1 7 7 3>;
    
    					adi,link-mode = <9>;			/* JESD Quick Configuration Mode */
    					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
    					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    					adi,dual-link = <0>;			/* JESD Dual Link Mode */
    
    					adi,converters-per-device = <8>;	/* JESD M */
    					adi,octets-per-frame = <4>;		/* JESD F */
    
    					adi,frames-per-multiframe = <64>;	/* JESD K */
    					adi,converter-resolution = <16>;	/* JESD N */
    					adi,bits-per-sample = <16>;		/* JESD NP' */
    					adi,control-bits-per-sample = <0>;	/* JESD CS */
    					adi,lanes-per-device = <4>;		/* JESD L */
    					adi,samples-per-converter-per-frame = <1>; /* JESD S */
    					adi,high-density = <0>;			/* JESD HD */
    
    					adi,tpl-phase-adjust = <0x3>;
    				};
    			};
    		};
    
    		adi,rx-adcs {
    			#size-cells = <0>;
    			#address-cells = <1>;
    
    			adi,adc-frequency-hz = /bits/ 64 <3932160000>;
                                                         
    			adi,main-data-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    
    				ad9081_adc0: adc@0 {
    					reg = <0>;
    					adi,decimation = <2>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <1000000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					adi,crossbar-select = <&ad9081_rx_fddc_chan0>;
    				};
    				ad9081_adc1: adc@1 {
    					reg = <1>;
    					adi,decimation = <2>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <1000000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					adi,crossbar-select = <&ad9081_rx_fddc_chan1>;
    				};
    				ad9081_adc2: adc@2 {
    					reg = <2>;
    					adi,decimation = <2>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <1000000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					adi,crossbar-select = <&ad9081_rx_fddc_chan4>;
    				};
    				ad9081_adc3: adc@3 {
    					reg = <3>;
    					adi,decimation = <2>;
    					adi,nco-frequency-shift-hz =  /bits/ 64 <1000000000>;
    					adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
    					adi,crossbar-select = <&ad9081_rx_fddc_chan5>;
    				};
    			};
    
    			adi,channelizer-paths {
    				#address-cells = <1>;
    				#size-cells = <0>;
    
    
    				ad9081_rx_fddc_chan0: channel@0 {
    					reg = <0>;
    					adi,decimation = <4>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan1: channel@1 {
    					reg = <1>;
    					adi,decimation = <4>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan4: channel@4 {
    					reg = <4>;
    					adi,decimation = <4>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    				ad9081_rx_fddc_chan5: channel@5 {
    					reg = <5>;
    					adi,decimation = <4>;
    					adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
    					adi,nco-frequency-shift-hz =  /bits/ 64 <0>;
    
    				};
    			};
    
    			adi,jesd-links {
    				#size-cells = <0>;
    				#address-cells = <1>;
    
    				ad9081_rx_jesd_l0: link@0 {
    					reg = <0>;
    					adi,converter-select =
    						<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
    						<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
    						<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
    						<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
    
    					adi,logical-lane-mapping = /bits/ 8 <2 0 7 7 7 7 3 1>;
    					//adi,logical-lane-mapping = /bits/ 8 <2 0 0 1 2 3 3 1>;
    
    					adi,link-mode = <10>;			/* JESD Quick Configuration Mode */
    					adi,subclass = <1>;			/* JESD SUBCLASS 0,1,2 */
    					adi,version = <2>;			/* JESD VERSION 0=204A,1=204B,2=204C */
    					adi,dual-link = <0>;			/* JESD Dual Link Mode */
    
    					adi,converters-per-device = <8>;	/* JESD M */
    					adi,octets-per-frame = <4>;		/* JESD F */
    
    					adi,frames-per-multiframe = <64>;	/* JESD K */
    					adi,converter-resolution = <16>;	/* JESD N */
    					adi,bits-per-sample = <16>;		/* JESD NP' */
    					adi,control-bits-per-sample = <0>;	/* JESD CS */
    					adi,lanes-per-device = <4>;		/* JESD L */
    					adi,samples-per-converter-per-frame = <1>; /* JESD S */
    					adi,high-density = <0>;			/* JESD HD */
    				};
    			};
    		};
    	};
    };
    

  • Have you been able to look into this?

  • I am attaching a simple dump of the MUX registers throughout the path in the AD9081 here for CDDC0 - FDDC0, CDDC1 - FDDC1, CDDC2 - FDDC4, CDDC3 - FDDC5. This was done to see whether there is any difference in how the data was routed till after the MUX4 between the single MXFE and Custom board.

    ********
    * MUX4 *	
    ******** 	
    
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0600 > direct_reg_access
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0601 > direct_reg_access
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x1
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0602 > direct_reg_access
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x2
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0603 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x3
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0604 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x8
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0605 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x9
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0606 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xA
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0607 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xB
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0608 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0609 > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060a > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060b > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060c > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060d > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060e > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x060f > direct_reg_access                                                                                            
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    
    
    
    ********
    * MUX3 *
    ********
    
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02a3 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02a8 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02ab > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02ac > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02ad > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x02ae > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    
    
    ********
    * MUX2 *
    ********
    
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0286 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x33
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0019 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0281 > direct_reg_access                         
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xAA
    
    
    ********
    * MUX1 *
    ********
    
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0280 > direct_reg_access  
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    
    
    ********
    * MUX0 *
    ********
    
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x001e 0x1 > direct_reg_access                                                                                 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0b12 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x4
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x001e 0x2 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# echo 0x0b12 > direct_reg_access 
    root@SPIU-AVRM:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x3
    
    
    
    
    ********
    * MUX4 *	
    ******** 	
    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0600 > direct_reg_access
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0601 > direct_reg_access
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x1
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0602 > direct_reg_access
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x2
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0603 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x3
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0604 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x8
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0605 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x9
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0606 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xA
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0607 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xB                                                                                       
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0608 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0609 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060a > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060b > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060c > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060d > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060e > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x060f > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    
    
    
    
    ********
    * MUX3 *
    ********
    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02a3 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02a8 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02ab > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02ac > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02ad > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x02ae > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    
    
    
    ********
    * MUX2 *
    ********
    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0286 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x33
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0019 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x80
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0281 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0xAA
    
    
    ********
    * MUX1 *
    ********
    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0280 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x0
    
    
    ********
    * MUX0 *
    ********
    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x001e 0x1 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0b12 > direct_reg_access 
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access 
    0x4
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x001e 0x2 > direct_reg_access                                                                                    
    root@zcu102:/sys/kernel/debug/iio/iio:device2# echo 0x0b12 > direct_reg_access                                                                                        
    root@zcu102:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access                                                                                    
    0x3
    
    
    


    Please go through and share your thoughts. Please note that this was taken from the single MXFE where 4 ADCs are working and custom board where only 2 ADCs were working. 

  • Hi, two device tree files are quite different but one of the first things I noticed in terms of the difference between them is the logical lane mapping. Could you review the logical lane mapping of the single mxfe?

  • The logical lane mapping was the default present in the zynqmp-zcu102-rev10-ad9081-m8-l4.dts

Reply Children
  • We have tried using the lane mapping for Tx and Rx in the zynqmp-zcu102-rev10-ad9081-m8-l4.dts for single MXFE in our Custom board ( The changes in the PHY IP for supporting this change in lane mapping was also done ). The test results revealed the same results where only ADC0 and ADC2 were working while ADC1 and ADC3 are still not working. However, The same lane mapping is functional when used on the single MXFE. I am unable to understand why same driver is giving two results with almost identical dtsi configurations. You had previously mentioned that there are differences between the two dtsi's. Could you point out the significant one's that should be noted.

  • We were using 4D4AB version of the chip for our custom board which is being reported to have the same issue i am facing if i understand correctly after going through the given discussion below. This means i was debugging a already reported issue you had previously discussed with somebody else.

    https://ez.analog.com/rf/wide-band-rf-transceivers/mixed-signal-front-ends-mxfe/f/q-a/587701/ad9081---enabling-8-fddc-in-rx-only-mode

  • Hi, sorry to hear of continuous trouble. As I understand, you have a single MxFE custom board that works as expected with the corresponding device tree. But you have trouble in getting the same results with multi MxFE custom board. Those two device tree look quite different, and not easy to follow for us. I am wondering why you cannot apply the the device tree that works on single MxFE to multi MxFE boad? 

  • We are using only one AD9081 on our custom board. All our hardware and layout design was done based on the single MXFE eval board to make it as identical as possible to the eval board. there is no multi-MXFE or multiple AD9081 being used on our custom board. Our clocking architecture is similar to the Quad MxFE to provide flexibility to provide higher clock rates to the ADC and DAC ( we use an additional ADF4377 PLL in line with the HMC7044 to get the AD9081 a clock of 11.79648 GHz without using the AD9081 internal PLL ).