When working with the AD9081 on my custom board, it is observed that only 2 lanes out of 4 configured for JESD data transmission seems to have valid data while rest show zeros. This data capture was observed using an ILA kept at the JESD RX within the PL section of the ZU15EG FPGA that i am working with. In addition to ILA, We also used indirect loopback to confirm the working channels ( ADC0 and ADC2 which are mapped to lanes 0 and 2 as mentioned in the dtsi attached ). To confirm that this is not an issue caused by power down of the ADCs ( RXEN based power saving ), a signal was fed through the ADC3 and routed through to the ADC0_x path using the MUX0 crossbar and looped back out through the DAC0 using indirect loopback. The data was observable in this case and a similar test case was done by routing the ADC1 through ADC0 ( Lane0 ). Both these tests ruled out the probability of the ADCs being in power down state.
The first picture on the left above shows our normal lane mapping ( Only 4 lanes are expected to be active for our current JESD configuration ). On the right is a test done to confirm whether there is a change in the lane on which data is placed. The test shows that the data is still on lane0 and lane2 on the AD9081 JESD side.
I would like to know what could be the cause for this rather weird scenario. Getting all the lanes to work is crucial in the scenario where we need all 4 ADCs to work simultaneously. Attaching the system-user.dtsi below. I am using petalinux-2022.1 and vivado 2022.1. The analog meta-adi linux kernel from github is being added as the meta-layer for the project and the 2022_R2 branch is being used.
/include/ "system-conf.dtsi" / { rx_fixed_linerate: clock@2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16220160>; clock-output-names = "rx_lane_clk"; }; tx_fixed_linerate: clock@3 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16220160>; clock-output-names = "tx_lane_clk"; }; fixed_clk: fixed-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1179620000>; clock-output-names = "support_clk"; }; adf4377_clkin: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <491520000>; }; clocks { adf4377_12000m: clock@1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <1179648000>; /* DAC_FREQUENCY / 10 */ //clock-frequency = <1179620000>; clock-output-names = "direct_clk_12000m"; }; }; }; #include <dt-bindings/iio/frequency/hmc7044.h> #include <dt-bindings/iio/adc/adi,ad9081.h> &gem0 { phy-mode = "sgmii"; is-internal-pcspma = "true"; fixed-link { speed = <1000>; full-duplex; }; }; &spi1 { status = "okay"; num-cs = <1>; hmc7044: hmc7044@0 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; compatible = "adi,hmc7044"; reg = <0>; spi-max-frequency = <100000>; jesd204-device; #jesd204-cells = <0x02>; jesd204-sysref-provider; adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */ adi,pll1-clkin-frequencies = <122880000 0 0 0>; adi,pll1-loop-bandwidth-hz = <200>; adi,vcxo-frequency = <122880000>; adi,pll1-charge-pump-current-ua = <720>; adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */ adi,pll2-output-frequency = <2949120000>; adi,sysref-timer-divider = <1024>; adi,pulse-generator-mode = <0>; adi,clkin0-buffer-mode = <0x7>; adi,oscin-buffer-mode = <0x7>; adi,gpi-controls = <0x00 0x00 0x00 0x00>; adi,gpo-controls = <0x7f 0x7f 0x00 0x00>; clock-output-names = "hmc7044_out0", "hmc7044_out1", "hmc7044_out2", "hmc7044_out3", "hmc7044_out4", "hmc7044_out5", "hmc7044_out6", "hmc7044_out7", "hmc7044_out8", "hmc7044_out9", "hmc7044_out10", "hmc7044_out11", "hmc7044_out12", "hmc7044_out13"; hmc7044_c0: channel@0 { reg = <0>; adi,extended-name = "RF_PLL_C_CLK"; adi,divider = <6>; /*49,15,20,000 491.51MHz*/ adi,driver-mode = <2>; }; hmc7044_c1: channel@1 { reg = <1>; adi,extended-name = "AD9081_C_CLK"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <2>; adi,jesd204-sysref-chan; }; hmc7044_c2: channel@2 { reg = <2>; adi,extended-name = "JESD_C_GTREFCLK1"; adi,divider = <12>; /*49,15,20,000 491.51MHz*/ adi,driver-mode = <2>; }; hmc7044_c3: channel@3 { reg = <3>; adi,extended-name = "C_FPGA_SYSREF1"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <2>; adi,jesd204-sysref-chan; }; hmc7044_c4: channel@4 { reg = <4>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; /* adi,extended-name = "JESD_C_GTREFCLK2"; adi,divider = <12>; adi,driver-mode = <2>; */ }; hmc7044_c5: channel@5 { reg = <5>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; /* adi,extended-name = "C_FPGA_SYSREF2"; adi,divider = <1536>; adi,driver-mode = <2>; adi,jesd204-sysref-chan; */ }; hmc7044_c6: channel@6 { reg = <6>; adi,extended-name = "JESD_C_DEVCLK1"; adi,divider = <12>; /*24,57,60,000 245.76MHz dont forget to change back to 6*/ adi,driver-mode = <2>; }; hmc7044_c7: channel@7 { reg = <7>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; adi,jesd204-sysref-chan; }; hmc7044_c8: channel@8 { reg = <8>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; /* adi,extended-name = "JESD_C_DEVCLK2"; adi,divider = <12>; adi,driver-mode = <2>; */ }; hmc7044_c9: channel@9 { reg = <9>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; adi,jesd204-sysref-chan; }; hmc7044_c10: channel@10 { reg = <10>; /* adi,extended-name = "UNUSED"; adi,divider = <1536>; adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; */ adi,extended-name = "RSVD_C_CLK_1"; adi,divider = <12>; adi,driver-mode = <2>; }; hmc7044_c11: channel@11 { reg = <11>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; adi,jesd204-sysref-chan; }; hmc7044_c12: channel@12 { reg = <12>; adi,extended-name = "UNUSED"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; /* adi,extended-name = "DBG_C_CLK"; adi,divider = <12>; adi,driver-mode = <2>; */ }; hmc7044_c13: channel@13 { reg = <13>; adi,extended-name = "DEV_CLK_DUP"; adi,divider = <1536>; /*19,20,000 1.92MHz*/ adi,driver-mode = <0>; adi,startup-mode-dynamic-enable; adi,driver-impedance-mode = <1>; adi,jesd204-sysref-chan; }; }; }; &jesd204c_axi_ad9081_rx_adc_tpl_core { compatible = "adi,axi-ad9081-rx-1.0"; reg = <0x0 0x80040000 0x0 0x10000>; /* dmas = <&rx_dma 0>; dma-names = "rx"; */ spibus-connected = <&trx0_ad9081>; jesd204-device; #jesd204-cells = <2>; jesd204-inputs = <&jesd204c_rx_axi 0 FRAMER_LINK0_RX>; }; &jesd204c_axi_ad9081_tx_dac_tpl_core { compatible = "adi,axi-ad9081-tx-1.0"; reg = <0x0 0x80050000 0x0 0x10000>; /* dmas = <&tx_dma 0>; dma-names = "tx"; */ clocks = <&trx0_ad9081 1>; clock-names = "sampl_clk"; spibus-connected = <&trx0_ad9081>; /* //adi,axi-pl-fifo-enable; adi,axi-data-offload-connected = <&axi_data_offload_tx>; */ jesd204-device; #jesd204-cells = <2>; jesd204-inputs = <&jesd204c_tx_axi 0 DEFRAMER_LINK0_TX>; }; &jesd204c_rx_axi { compatible = "adi,axi-jesd204-rx-1.0"; reg = <0x0 0x80010000 0x0 0x10000>; interrupts = <0 90 4>; clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&rx_fixed_linerate 0>; clock-names = "s_axi_aclk", "device_clk", "lane_clk"; #clock-cells = <0>; clock-output-names = "jesd_rx_lane_clk"; jesd204-device; #jesd204-cells = <2>; jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>; }; &jesd204c_tx_axi { compatible = "adi,axi-jesd204-tx-1.0"; reg = <0x0 0x80020000 0x0 0x10000>; interrupts = <0 89 4>; clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&tx_fixed_linerate 0>; clock-names = "s_axi_aclk", "device_clk", "lane_clk"; #clock-cells = <0>; clock-output-names = "jesd_tx_lane_clk"; jesd204-device; #jesd204-cells = <2>; jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>; }; &spi0 { is-decoded-cs = <0>; num-cs = <2>; status = "okay"; trx0_ad9081:ad9081@0 { #address-cells = <1>; #size-cells = <0>; compatible = "adi,ad9081"; reg = <0>; spi-max-frequency = <5000000>; //clocks = <&fixed_clk 0>; //clock-names = "support_clk"; // clocks = <&hmc7044 0>; // clock-names = "dev_clk"; //clocks = <&adf4377>; //clock-names = "dev_clk"; // clocks = <&adf4377_12000m>; /* dev_clk 11796480000Hz */ dev_clk-clock-scales = <1 10>; clock-names = "dev_clk"; clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; #clock-cells = <1>; jesd204-device; #jesd204-cells = <2>; jesd204-top-device = <0>; /* This is the TOP device */ jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>; jesd204-ignore-errors;//TODO DEBUG ONLY REMOVE LATER jesd204-inputs = <&jesd204c_axi_ad9081_rx_adc_tpl_core 0 FRAMER_LINK0_RX>, <&jesd204c_axi_ad9081_tx_dac_tpl_core 0 DEFRAMER_LINK0_TX>; adi,tx-dacs { #size-cells = <0>; #address-cells = <1>; adi,dac-frequency-hz = /bits/ 64 <11796480000>; adi,main-data-paths { #address-cells = <1>; #size-cells = <0>; adi,interpolation = <6>; ad9081_dac0: dac@0 { reg = <0>; adi,crossbar-select = <&ad9081_tx_fddc_chan0>; adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */ }; ad9081_dac1: dac@1 { reg = <1>; adi,crossbar-select = <&ad9081_tx_fddc_chan1>; adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */ }; ad9081_dac2: dac@2 { reg = <2>; adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */ adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */ }; ad9081_dac3: dac@3 { reg = <3>; adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */ adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */ }; }; adi,channelizer-paths { #address-cells = <1>; #size-cells = <0>; adi,interpolation = <4>; ad9081_tx_fddc_chan0: channel@0 { reg = <0>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_tx_fddc_chan1: channel@1 { reg = <1>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_tx_fddc_chan2: channel@2 { reg = <2>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_tx_fddc_chan3: channel@3 { reg = <3>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; }; adi,jesd-links { #size-cells = <0>; #address-cells = <1>; ad9081_tx_jesd_l0: link@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>; adi,link-mode = <9>; /* JESD Quick Configuration Mode */ adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */ adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */ adi,dual-link = <0>; /* JESD Dual Link Mode */ adi,converters-per-device = <8>; /* JESD M */ adi,octets-per-frame = <4>; /* JESD F */ adi,frames-per-multiframe = <64>; /* JESD K */ adi,converter-resolution = <16>; /* JESD N */ adi,bits-per-sample = <16>; /* JESD NP' */ adi,control-bits-per-sample = <0>; /* JESD CS */ adi,lanes-per-device = <4>; /* JESD L */ adi,samples-per-converter-per-frame = <1>; /* JESD S */ adi,high-density = <0>; /* JESD HD */ adi,tpl-phase-adjust = <0x3>; }; }; }; adi,rx-adcs { #size-cells = <0>; #address-cells = <1>; adi,adc-frequency-hz = /bits/ 64 <3932160000>; adi,main-data-paths { #address-cells = <1>; #size-cells = <0>; ad9081_adc0: adc@0 { reg = <0>; adi,decimation = <4>; adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>; //adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */ }; ad9081_adc1: adc@1 { reg = <1>; adi,decimation = <4>; adi,nco-frequency-shift-hz = /bits/ 64 <(100000000)>; adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>; //adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */ }; ad9081_adc2: adc@2 { reg = <2>; adi,decimation = <4>; adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>; //adi,crossbar-select = <&ad9081_rx_fddc_chan4>, <&ad9081_rx_fddc_chan6>; /* Static for now */ }; ad9081_adc3: adc@3 { reg = <3>; adi,decimation = <4>; adi,nco-frequency-shift-hz = /bits/ 64 <100000000>; adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>; //adi,crossbar-select = <&ad9081_rx_fddc_chan5>, <&ad9081_rx_fddc_chan7>; /* Static for now */ }; }; adi,channelizer-paths { #address-cells = <1>; #size-cells = <0>; ad9081_rx_fddc_chan0: channel@0 { reg = <0>; adi,decimation = <2>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_rx_fddc_chan1: channel@1 { reg = <1>; adi,decimation = <2>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_rx_fddc_chan4: channel@4 { reg = <4>; adi,decimation = <2>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; ad9081_rx_fddc_chan5: channel@5 { reg = <5>; adi,decimation = <2>; adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */ adi,nco-frequency-shift-hz = /bits/ 64 <0>; }; }; adi,jesd-links { #size-cells = <0>; #address-cells = <1>; ad9081_rx_jesd_l0: link@0 { reg = <0>; adi,converter-select = <&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>, <&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>, <&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>, <&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>; adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>; adi,link-mode = <10>; /* JESD Quick Configuration Mode */ adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */ adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */ adi,dual-link = <0>; /* JESD Dual Link Mode */ adi,converters-per-device = <8>; /* JESD M */ adi,octets-per-frame = <4>; /* JESD F */ adi,frames-per-multiframe = <64>; /* JESD K */ adi,converter-resolution = <16>; /* JESD N */ adi,bits-per-sample = <16>; /* JESD NP' */ adi,control-bits-per-sample = <0>; /* JESD CS */ adi,lanes-per-device = <4>; /* JESD L */ adi,samples-per-converter-per-frame = <1>; /* JESD S */ adi,high-density = <0>; /* JESD HD */ }; }; }; }; spidev@1 { compatible = "lwn,bk4"; reg = <1>; status = "okay"; spi-max-frequency = <10000000>; }; };
lane number correction
[edited by: AflahAfu at 6:25 PM (GMT -5) on 22 Nov 2024]