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ADs MxFE JESD204 mode selector tool doesn't work!

Category: Software

Dear, 

I have an AD9082 evaluation board, struggling with selecting the right JESD mode and clock configuration. It's necessary in order to implement different decimation and interpolations.

The datasheet refers the users to ADs MxFE JESD204 mode selector tool (python-based SW). However, the tool doesn't work and crashes all the time with the same error message. 

See the example below.

************************************

Analog Devices Inc
Revision date Mar 2022
Revision PrD
A series of prompts will help narrow down the usable
JESD204 modes supported by the MxFE platform.
**********************************************************
Please select product
1 AD9081
2 AD9082
3 AD9986
4 AD9988
5 AD9207
6 AD9209
7 AD9177
Enter index of selection
2
How many Fine Digital Up-Converter (FDUC) are used? (0 to bypass, up to 8)
2
How many Fine Digital Down-Converter (FDDC) are used? (0 to bypass, up to 8)
2
For Tx, consider the following modes:
1 Single Link
2 Dual Link
3 Single And Dual Link
Enter index of selection
1
For Rx, consider the following modes:
1 Single Link
2 Dual Link
3 Single And Dual Link
Enter index of selection
1
Select the following JESD modes to include
1 JESD204B
2 JESD204C
3 JESD204B AND JESD204C
Enter index of selection
1
Please enter desired Tx Sample rate (GSPS) [2.9-12]
12
Please enter min Tx instantaneous Bandwidth (MHz) (600MHz max):
375
Please choose Rx Sample Rate from these Tx clock division options (GSPS) [1.45-6]:
1 6.0
2 4.0
3 3.0
Enter index of selection
1
Please enter min Rx instantaneous Bandwidth (MHz) (610MHz max):
375

Supported Tx Lane rates (GBPS): []
Supported Rx Lane rates (GBPS): []

There are no compatible Lane Rates, loosen constraints and try again
Traceback (most recent call last):
File "JESD_Mode_Helper.py", line 506, in <module>
File "JESD_Mode_Helper.py", line 483, in masterloop
TypeError: cannot unpack non-iterable NoneType object
[12964] Failed to execute script 'JESD_Mode_Helper' due to unhandled exception!

***********************************

Could you please me with this?

  • I see an issue in the tool with the parameters you entered, which is being examined by the team now. Will provide an update shortly.

  • Just to let you know that tool group is notified and they are working on the fix. In the meantime, you can bypass FDDC and FDUC to get a sensible results from the tool.

  • Thank you very much for the update. Looking forward to having a fully operational tool. Our application requires various decimation and interpolation rates which are not possible without DDC and DUC.

  • PrF version is up on the web, which should provide a meaningful results to your input parameters. Please try it and let us know.

  • Thanks for the update. I managed to test the PrF version. It works fine when you don't have any "Fine Down/Up converter".

    But as soon as I tried to run it for a case with a fine converter, it could not generate meaningful output. 

    For instance, I have a working device tree for the case below that sets Tx to mode 15 and Rx to mode 18. 

    Interpolation: 12 x 2, Decimation: 6 x 2, DAC freq: 12G, ADC freq: 6G.

    I expect some results from the tool but I think it still has problems.

    Analog Devices Inc
    Revision date Mar 2022
    Revision PrD
    A series of prompts will help narrow down the usable
    JESD204 modes supported by the MxFE platform.
    **********************************************************
    Please select product
    1 AD9081
    2 AD9082
    3 AD9986
    4 AD9988
    5 AD9207
    6 AD9209
    7 AD9177
    Enter index of selection
    2
    How many Fine Digital Up-Converter (FDUC) are used? (0 to bypass, up to 8)
    1
    How many Fine Digital Down-Converter (FDDC) are used? (0 to bypass, up to 8)
    1
    For Tx, consider the following modes:
    1 Single Link
    2 Dual Link
    3 Single And Dual Link
    Enter index of selection
    3
    For Rx, consider the following modes:
    1 Single Link
    2 Dual Link
    3 Single And Dual Link
    Enter index of selection
    3
    Select the following JESD modes to include
    1 JESD204B
    2 JESD204C
    3 JESD204B AND JESD204C
    Enter index of selection
    3
    Please enter desired Tx Sample rate (GSPS) [2.9-12]
    12
    Please enter min Tx instantaneous Bandwidth (MHz) (600MHz max):
    500
    Please choose Rx Sample Rate from these Tx clock division options (GSPS) [1.45-6]:
    1 6.0
    2 4.0
    3 3.0
    Enter index of selection
    1
    Please enter min Rx instantaneous Bandwidth (MHz) (610MHz max):
    500

    Supported Tx Lane rates (GBPS): []
    Supported Rx Lane rates (GBPS): []

    There are no compatible Lane Rates, loosen constraints and try again
    Traceback (most recent call last):
    File "JESD_Mode_Helper.py", line 506, in <module>
    File "JESD_Mode_Helper.py", line 483, in masterloop
    TypeError: cannot unpack non-iterable NoneType object
    [453040] Failed to execute script 'JESD_Mode_Helper' due to unhandled exception!

  • Thank you for your feedback. I also noticed that it doesn't produce any output if number of FDUC and FDDC is 1, but it works well if they are zeros or higher than 1. Please try to use 2 or higher FDUC and FDDC if you need channelizer, and I'll keep look at the issue with 1.