My company build a board based on AD9081. It seems the 204B links(we tested use case 23 only) are not stable，expecially on the DAC path. The syncb signal keeps getting up and down in a random pattern.
FPGA board we are using is Xilinx ZCU102. And the 204IP, PHY IP are from xilinx too. We have used the same design with a ad9009 evaluation board, and there is no such problem.
One interesting finding is that the PRBS test is not convincible. The JRX side is set to detect PRBS7 or PRBS31.
1. When there is no signal at all on the lanes, the bit 6 on JRX_TEST_3_LANEn still shows the PRBS is locked. The error count is 0xFFFFFF, the maximum number.
2. When FPGS send PRBS on some lanes, the PRBS error count is around 1.0e6 every second for 10G lane rate.
Do you have any suggestion on how to go on the debug?