HI,
I am having trouble controlling JESD204B in AD9081.
The JESD204B Setting for controlling the four DACs is as follows.
JESD MODE 16
L 8
M 16
F 4
S 1
K 32
N 16
Daterate 250MSPS
Lanerate 10GHz
TOTAL_INTEPOLATION 12x4
The JESD204B structure I think is as shown in the figure.
| (L = 8, M = 16, F = 4, S = 1, NP = 16) | ||||
| Frame 0 | ||||
| Lanes | Octet 0 | Octet 1 | Octet 2 | Octet 3 |
| 0 | M0S0[15:8] | M0S0[7:0] | M1S0[15:8] | M1S0[7:0] |
| 1 | M2S0[15:8] | M2S0[7:0] | M3S0[15:8] | M3S0[7:0] |
| 2 | M4S0[15:8] | M4S0[7:0] | M5S0[15:8] | M5S0[7:0] |
| 3 | M6S0[15:8] | M6S0[7:0] | M7S0[15:8] | M7S0[7:0] |
| 4 | M8S0[15:8] | M8S0[7:0] | M9S0[15:8] | M9S0[7:0] |
| 5 | M10S0[15:8] | M10S0[7:0] | M11S0[15:8] | M11S0[7:0] |
| 6 | M12S0[15:8] | M12S0[7:0] | M13S0[15:8] | M13S0[7:0] |
| 7 | M14S0[15:8] | M14S0[7:0] | M15S0[15:8] | M15S0[7:0] |
case : tx_start_of_frame [0001]
This is the JESD204 IP setting that I set.
If I send DATA to a specific TDATA,
EX) TDATA[127:96] <= IQ_DATA else ALL 0 input
The frequency moves normally by the value the output sent to TDATA.
Sending all of the DATA to TDATA[255:0] results in a strange output, just as multiple frequencies come out at the same time.
Is the structure I'm thinking wrong?
Or is there anything I can think of?