AD9081 Examples using the on-chip PLL?

Hi youngpines,

Thanks for your post. I'll try to get back to you within a day or so regarding this. I apologize for the delay.

Doug

Thanks! I've added some more detail about what I'm seeing on the bench

Hi youngpines,

Thank you very much for the detailed information. On paper, first pass, it looks to me like your target configuration should work. I have no explanation on the L = 1 value, or the strange frequency you are observing on the ADC_CLK terminal on the board.

I'll try to get to the lab within the next 2 days to:

• try to replicate your configuration
• hopefully come up with a working example for you to try

Thank you.

Doug

Hi youngpines,

I tried your configuration. I got the same result as you in ACE. The red Rx ILAS error LED was lit. The spectrum analyzer by my bench only goes up to 2.9GHz so I did not look at the frequency on the ADC_CLK pin.

It seems like ACE reacted by giving an error when I changed the Rx decimation to 2x, but I did not investigate the reason for the failure. Instead I looked for a configuration that worked with the PLL.

This configuration worked for me:

I don't know if this is close to a configuration you are interested in, but at least it is an example of a configuration working with the clock multiplier PLL (at least on my bench).

Does this configuration work for you?

Thanks,

Doug

Hi again,

The image I copied and pasted into my reply above was large and legible. When I tried to read it after posting, it was not legible. I'm sorry about that. Let's try this:

Doug

Hi Doug, 

Thanks for the help so far! I wanted to ask if this configuration has a PLL lock consistently after power cycles. I found the on-chip PLL came up once but still acts weirdly and inconsistently.

I did the following

1. Enabled the on-chip PLL in the configuration you showed.
   1. All link statuses were green! (JESD PLL, JESD RX, JESD TX, On-Chip PLL lock) Temperature readings were available
   2. 375 MHz reference is clocking the FPGA and dataconveter
   3. ADC_CLKOUT output is 3.903 GHz. I expected something closer to 4 GHz
   4. I couldn't replicate this again
2. Power cycled the setup and tried (1) again.
   1. JESD PLL status is green but (On-chip PLL lock, JESD RX, JESD RX) status is all down, no temperature readings available
   2. 375 MHz reference is clocking the FPGA and dataconveter
3. I tried the same settings in direct clocking mode, disabling the on-chip PLL.
   1. All link statuses green except the on-chip PLL since I'm bypassing it here
   2. 375 MHz reference is clocking the FPGA, 12 GHz signal is clocking the dataconveter
   3. ADC_CLKOUT output is 3.996 GHz. This is closer to the expected 4 GHz
4. Tried enabling the on-chip PLL again, same as (1)
   1. JESD PLL status is green but (On-chip PLL lock, JESD RX, JESD RX) status is all down, no temperature readings available
   2. 375 MHz reference is clocking the FPGA and dataconveter
   3. ADC_CLKOUT output is 8.042GHz

In situation (4), I saw similar things as my original post where the ACE window looked like the following

and the PLL registers read 

• 0x00E3 shows R = 1
• 0x0093 shows D = 1
• 0x00E9 shows N = 4
• 0x00EC shows M = 8
• 0x0180 shows L = 1 (This is weird, I expected L = 3)
• 0x2008 shows the PLL is not locked fast or slow
  • This is different from my original post

I turned off both 375 MHz reference inputs to the dataconverter and FPGA, and the 8.042 GHz signal on the ADC output didn't go away and stayed at the same power level. This output frequency also doesn't change when the 375 MHz reference is adjusted (e.g. to 350 MHz or 450 MHz). The picture shows the spectrum when the 375 MHz references were on enabled, disabled, or adjusted.

To verify the 375 MHz input clock was getting in the loop, I set PD_ADC_DRIVER=0 in register 0x0198 and set PLL_BYPASS=1 in register 0x0094. I then connected ADC_CLKOUT on the AD9081 evaluation board to a spectrum analyzer. 

I think the VCO may be free-runnning for some reason.

HI youngpines,

I'm sorry about the inconsistencies!

When I went through this exercise I first found a configuration that worked with the evaluation board configured for external clock. Then I used the same configuration except I used the internal PLL, specified a 375MHz PLL reference, and it came up right away (after I remembered to turn on the signal generators ). Because it came up right away first time, I thought it was robust but I did not try it multiple times. It was a bad assumption on my part.

I haven't been back in the lab since I tried that last configuration. I'll try to go back in the next day or so and try it again.

Doug

Hi Doug,

I think I was able to track down why this path doesn't work. The external clock input goes to a BAL-0416SMG balun whose frequency range is 4-16 GHz so there's significant attenuation at inputs < 1 GHz.

I wanted to use a custom reference frequency and the on-chip PLL to bring that up to my expected configuration. I tried using the EXT_REF connection for the HMC7044 but got many errors that the "index was out of range" for anything other than 100 MHz

Is there an example that changes the "HMC7044 Clock Input" to something other than 100 MHz I could try or is that not supported by this board?

Thanks for all the help so far! I appreciate it a lot.

Hi youngpines,

Yes, the frequency range of the clock balun is an issue at lower frequencies, but because you were observing 375MHz on the ADC_CLK pin I thought this might not be what was causing your issue.

We'll sometimes use higher signal generator power to "brute force" a lower frequency through the balun.

Is 375MHz your preferred target PLL reference frequency?

What power setting were you using on your PLL reference signal generator?

Thanks,

Doug

Hi Doug,

When I had the 375 MHz reference in the dataconverter, I tried outputting +5 dBm to +11 dBm from my signal generator to the board.

I found +11 dBm by looking at the clock the dataconverter received when bypassing the PLL and setting L=1 and seeing when increasing the power didn't increase the fundamental frequency's power much. My coax cable is only ~a foot long and has <1 dB loss.

I originally wanted to try these settings out that uses a 234.375 MHz reference clock. Please ignore the "Clock Source" settings I have in the picture. Would you be able to suggest how to try this out?

Thanks again!