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AD9207 FD_DWELL_THRESH_UP registers not described in UG-1578


UG-1578 shows two registers FD_DWELL_THRESH_UP_LSB and FD_DWELL_THRESH_UP_MSB on page 153.  

I cannot find any explanation as to what these registers do in UG-1578. (Apologies if I'm mistaken).

What is the purpose of FD_DWELL_THRESH_UP and does it apply to both FD0 and FD1?


Parents Reply
  • Hi,

    I have confirmed API details with the team. FD0_FUNC_SEL (bit 4 of register 0x0352) needs to be set separately by user in the API. In other words, the steps to use the upper threshold are:

    1. Use the adi_txfe_adc_fd_thresh_set function to set up threshold. The parameters are 16-bit so LSB and MSB are already accounted for

    2. Use adi_txfe_adc_fd0_function_mode_set to set the fd0_func_sel bit