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AD9207 FD_DWELL_THRESH_UP registers not described in UG-1578


UG-1578 shows two registers FD_DWELL_THRESH_UP_LSB and FD_DWELL_THRESH_UP_MSB on page 153.  

I cannot find any explanation as to what these registers do in UG-1578. (Apologies if I'm mistaken).

What is the purpose of FD_DWELL_THRESH_UP and does it apply to both FD0 and FD1?


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  • Hi Judy. 

    Thanks for looking into this for me.

    Line 2634 of the HAL (adi_ad9207_adc) suggests that FD_DWELL_THRESH_UP_LSB is only for FD1, but the HAL never sets FD_DWELL_THRESH_UP_MSB (register 0x033A). 

    Does FD_DWELL_THRESH_UP_MSB and  FD_DWELL_THRESH_UP_LSB only apply to FD1 or is the HAL incorrect and missing functionality?

    Also, when will UG-1578 be updated.  It is out of date with respect to the HAL.


  • Hi,

    I have updated the UG-1578 to reflect the information in this ezone thread. UG-1578 is now sitting in our technical documentation queue along with other changes to be made. I would anticipate the update document to be published with the next two months.

    I am checking with the API team to confirm the code and register details. I will let you know when I hear back. 


  • Hi,

    I have confirmed API details with the team. FD0_FUNC_SEL (bit 4 of register 0x0352) needs to be set separately by user in the API. In other words, the steps to use the upper threshold are:

    1. Use the adi_txfe_adc_fd_thresh_set function to set up threshold. The parameters are 16-bit so LSB and MSB are already accounted for

    2. Use adi_txfe_adc_fd0_function_mode_set to set the fd0_func_sel bit


  • Thanks Judy.  I think I understand.  So setting adc_fd0_function_mode_set and adc_fd1_function_mode_set  can enable the use of the values in  registers FD_DWELL_THRESH_UP_LSB and FD_DWELL_THRESH_UP_MSB.  I take it that this means that independent dwell_thresh_up values cannot be set for FD0 and FD1?