AD9207 FD_DWELL_THRESH_UP registers not described in UG-1578

Hi,

I have found the register to enable the upper threshold for FD0. Please see register description below.

Register 0x0352 Bit 4:

Judy

Hi,

I have found the register to enable the upper threshold for FD0. Please see register description below.

Register 0x0352 Bit 4:

Judy

Hi Judy. 

Thanks for looking into this for me.

Line 2634 of the HAL (adi_ad9207_adc) suggests that FD_DWELL_THRESH_UP_LSB is only for FD1, but the HAL never sets FD_DWELL_THRESH_UP_MSB (register 0x033A). 

Does FD_DWELL_THRESH_UP_MSB and  FD_DWELL_THRESH_UP_LSB only apply to FD1 or is the HAL incorrect and missing functionality?

Also, when will UG-1578 be updated.  It is out of date with respect to the HAL.

Thanks.

Hi,

I have updated the UG-1578 to reflect the information in this ezone thread. UG-1578 is now sitting in our technical documentation queue along with other changes to be made. I would anticipate the update document to be published with the next two months.

I am checking with the API team to confirm the code and register details. I will let you know when I hear back. 

Judy

Hi,

I have confirmed API details with the team. FD0_FUNC_SEL (bit 4 of register 0x0352) needs to be set separately by user in the API. In other words, the steps to use the upper threshold are:

1. Use the adi_txfe_adc_fd_thresh_set function to set up threshold. The parameters are 16-bit so LSB and MSB are already accounted for

2. Use adi_txfe_adc_fd0_function_mode_set to set the fd0_func_sel bit

Judy

Thanks Judy.  I think I understand.  So setting adc_fd0_function_mode_set and adc_fd1_function_mode_set  can enable the use of the values in  registers FD_DWELL_THRESH_UP_LSB and FD_DWELL_THRESH_UP_MSB.  I take it that this means that independent dwell_thresh_up values cannot be set for FD0 and FD1?