Mixed-Signal Front Ends (MxFE)

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by jwilcox
Mixed-Signal Front Ends (MxFE)

3 hours ago
85 9 0
Not Answered
AD9081 Evaluation Board HMC7044 Configuration Errors 0
Not Answered

I am trying to use the AD9081-FMCA-EBZ evaluation board to test a few JESD204C configurations. However, when I try to do any chip view configurations, I receive Error Code: -14 and a notice is displayed that there is a problem with configuring the HMC7044...

Clock Generation Devices Clock Generation and Distribution hmc7044 software AD9081 ACE 1.30.3369.1491 AD9081-FMCA-EBZ High Speed A/D Converters >10 MSPS jesd204c Mixed-Signal Front Ends (MxFE) AD9081_FMCA_EBZ Show More

85 9 0
by Oceanman
Mixed-Signal Front Ends (MxFE)

2 days ago
24 1 0
Not Answered
Can AD9081 sample output DAC port? 0
Not Answered

Hi, I wonder if AD9081 has a build-in sampling port to sample the output signal from DAC. It would be great if we can monitor8 the reference signal without external directional coupler. Thank you!

hardware High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE)

24 1 0
by Khyaati
Mixed-Signal Front Ends (MxFE)

3 days ago
37 1 0
Not Answered
Custom FPGA solution with AD9082-FMCA-EBZ 0
Not Answered

Dear Team, Greetings of the day! I am willing to make a custom FPGA board with ZU19EG FPGA. I was wondering if the AD9082-FMCA-EBZ can be used with it. We intend to make a custom FPGA board with ZU19EG. Can you confirm the integration of ZU19EG...

hardware High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9082

37 1 0
by UVLSIDRIVER
Mixed-Signal Front Ends (MxFE)

3 days ago
91 5 0
Not Answered
Guidance on Increasing DAC Output Current in AD9082 0
Not Answered

Hi, I am currently working with the AD9082 and focusing on the DAC output performance. By default, the DAC output current is set to 26 mA , which is configurable via registers 0x0117 and 0x0118 . According to the datasheet, this current can be adjusted...

vivado 2018.3 software High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9082 dac_current Show More

91 5 0
by SAH
Mixed-Signal Front Ends (MxFE)

4 days ago
259 20 0
Answered
AD9082 reference HDL, TPL core IQ ports +1
Answered

Dear, We are working with an AD9082 MxFE evaluation board and the reference HDL design for the Xilinx ZCU102. In our test setup, we feed an OQPSK IQ stream into DAC0. In the HDL design, the in-phase (I) samples are connected to dac_data0 , and the...

hardware High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE)

259 20 0
by Oceanman
Mixed-Signal Front Ends (MxFE)

7 days ago
115 6 0
Answered
ZCU102 + AD9081 JESD disabled after properly functioning +1
Answered

Hi, I am running a MATLAB file that emit a 10GHz signal. It has been working properly for a while, and the antenna lost the 5V connection in the middle of it. After running the jesd_status command, I found that the jesd is disabled. When we are...

hardware High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE)

115 6 0
by AflahAfu
Mixed-Signal Front Ends (MxFE)

10 days ago
102 3 0
Not Answered
Multi-board chip synchronization 0
Not Answered

I am trying to synchronize two boards each having a HMC7044 + AD9081 similar to what is on the Quad MXFE ( We also have a ADF4377 in between the HMC and AD9081 but it is bypassed now to use internal PLL of the AD9081 ). My understanding is that when the...

Clock Generation Devices Clock Generation and Distribution software 2023_R2 linux AD9081 High Speed A/D Converters >10 MSPS Phase Locked Loop with Integrated VCO Mixed-Signal Front Ends (MxFE) Show More

102 3 0
by daedalus
Mixed-Signal Front Ends (MxFE)

15 days ago
646 10 1
Answered
AD9082 JESD204C link fails when changing decimation ratio at runtime +1
Answered

Hi. I am using the AD9082 in dual link mode. I would like to change the decimation ratio of the FDDC on the fly, without changing the JESD204C data rate. The AD9082 supports this for power of two decimation ratios, as it can repeat samples using the...

High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9082

646 10 1
by UVLSIDRIVER
Mixed-Signal Front Ends (MxFE)

15 days ago
25 0 0
Not Answered
AD9081 DAC Output Variation with Different Interpolation Factor Combinations 0
Not Answered

hello

software AD9081 High Speed A/D Converters >10 MSPS sdk 2018.3 Mixed-Signal Front Ends (MxFE) Show More

25 0 0
by Khyaati
Mixed-Signal Front Ends (MxFE)

16 days ago
51 1 0
Not Answered
Analog Bandwidth of DAC 0
Not Answered

Hi Team, Greetings of the Day! I am intending to use the AD9082 in my application. I am writing to seek your guidance regarding the DAC Analog Bandwidth Range. The Analog Bandwidth Range of AD9082 is mentioned as: 8GHZ The Sampling Rate is 12GSPS...

Datasheet/Specs High Speed A/D Converters >10 MSPS Mixed-Signal Front Ends (MxFE) AD9082

51 1 0

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Mixed-Signal Front Ends (MxFE)

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AD9081 Evaluation Board HMC7044 Configuration Errors 0
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Can AD9081 sample output DAC port? 0
Not Answered

Not Answered
Custom FPGA solution with AD9082-FMCA-EBZ 0
Not Answered

Not Answered
Guidance on Increasing DAC Output Current in AD9082 0
Not Answered

Answered
AD9082 reference HDL, TPL core IQ ports +1
Answered

Answered
ZCU102 + AD9081 JESD disabled after properly functioning +1
Answered

Not Answered
Multi-board chip synchronization 0
Not Answered

Answered
AD9082 JESD204C link fails when changing decimation ratio at runtime +1
Answered

Not Answered
AD9081 DAC Output Variation with Different Interpolation Factor Combinations 0
Not Answered

Not Answered
Analog Bandwidth of DAC 0
Not Answered

Answered
ZCU102 + AD9081 JESD disabled after properly functioning +1
Answered

Answered
AD9082 reference HDL, TPL core IQ ports +1
Answered

Answered
ADS9+AD9986 and APIs 0
Answered

Answered
Weird ADC samples from AD9081 0
Answered

Answered
linux api 0
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Interfacing HMC7044B with ADF4368 - EZSync 0
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Answered
Spectral inversion feature of AD9082 +1
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Register Map 0
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AD9082 ADC path not working 0
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Answered
AD9081 + ZC706 Set Lane Rate Failed when Changing Device Clock Frequency 0
Answered

Mixed-Signal Front Ends (MxFE)

Not Answered AD9081 Evaluation Board HMC7044 Configuration Errors 0 Not Answered

Not Answered Can AD9081 sample output DAC port? 0 Not Answered

Not Answered Custom FPGA solution with AD9082-FMCA-EBZ 0 Not Answered

Not Answered Guidance on Increasing DAC Output Current in AD9082 0 Not Answered

Answered AD9082 reference HDL, TPL core IQ ports +1 Answered

Answered ZCU102 + AD9081 JESD disabled after properly functioning +1 Answered

Not Answered Multi-board chip synchronization 0 Not Answered

Answered AD9082 JESD204C link fails when changing decimation ratio at runtime +1 Answered

Not Answered AD9081 DAC Output Variation with Different Interpolation Factor Combinations 0 Not Answered

Not Answered Analog Bandwidth of DAC 0 Not Answered

Answered ZCU102 + AD9081 JESD disabled after properly functioning +1 Answered

Answered AD9082 reference HDL, TPL core IQ ports +1 Answered

Answered ADS9+AD9986 and APIs 0 Answered

Answered Weird ADC samples from AD9081 0 Answered

Answered linux api 0 Answered

Answered Interfacing HMC7044B with ADF4368 - EZSync 0 Answered

Answered Spectral inversion feature of AD9082 +1 Answered

Answered Register Map 0 Answered

Answered AD9082 ADC path not working 0 Answered

Answered AD9081 + ZC706 Set Lane Rate Failed when Changing Device Clock Frequency 0 Answered

Not Answered
AD9081 Evaluation Board HMC7044 Configuration Errors 0
Not Answered

Not Answered
Can AD9081 sample output DAC port? 0
Not Answered

Not Answered
Custom FPGA solution with AD9082-FMCA-EBZ 0
Not Answered

Not Answered
Guidance on Increasing DAC Output Current in AD9082 0
Not Answered

Answered
AD9082 reference HDL, TPL core IQ ports +1
Answered

Answered
ZCU102 + AD9081 JESD disabled after properly functioning +1
Answered

Not Answered
Multi-board chip synchronization 0
Not Answered

Answered
AD9082 JESD204C link fails when changing decimation ratio at runtime +1
Answered

Not Answered
AD9081 DAC Output Variation with Different Interpolation Factor Combinations 0
Not Answered

Not Answered
Analog Bandwidth of DAC 0
Not Answered

Answered
ZCU102 + AD9081 JESD disabled after properly functioning +1
Answered

Answered
AD9082 reference HDL, TPL core IQ ports +1
Answered

Answered
ADS9+AD9986 and APIs 0
Answered

Answered
Weird ADC samples from AD9081 0
Answered

Answered
linux api 0
Answered

Answered
Interfacing HMC7044B with ADF4368 - EZSync 0
Answered

Answered
Spectral inversion feature of AD9082 +1
Answered

Answered
Register Map 0
Answered

Answered
AD9082 ADC path not working 0
Answered

Answered
AD9081 + ZC706 Set Lane Rate Failed when Changing Device Clock Frequency 0
Answered