On a hardware setup that is close to a ZCU102 evaluation system with essentially an ADI Reference FPGA design, FDD works fine, as does TDD when using a TDD Profile, but the use of a Frequency Hopping Profile results in TX1 getting stuck in RF-Enabled when applying a TX_Setup signal.
I use Linux, ADRV9001 SDK and a HAL to communicate with ADRV9002. When diffing the two json files of the Profiles, the main difference is the setting of the 'fhModeOn' parameter. I use the attributes that the TDD driver presents to sysfs to generate TX_Setup and RX_Setup signals, and some simple FPGA logic for HOP1 generation. All 3 signals are timed relative to a TDD Sync signal. Using an oscilloscope to probe the Setup and HOP signals at the ADRV9002 Eval Board, I've confirmed that the relationship of the Setup and HOP signals is appropriate when compared to UG-1828 guidelines. The same Setup and HOP signals are used with both profiles, so I don't believe the issue is with the signals or the FH profile. Besides using TES to generate the profiles, I use TES to generate associated stream images. Could my FH stream image be faulty somehow resulting in the stuck channel? Any suggestions on where else to look for problems would be much appreciated. Thanks, Mike