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zc706 + adrv9009 400mhBW

software on Nov 10, 2025

Thread Summary

The user asked if the ZC706 with ADRV9009 can support 400 MHz bandwidth on ORx and Tx channels. The final answer suggests modifying the HDL script to change the QPLL feedback divider and updating the device tree to set the channel divider to 5 for all channels. Alternatively, the user can adjust the interpolation filter configuration by doubling the frequency values. The user should ensure the XCVR_QPLL is used for all links and provide a JESD log/status for further troubleshooting.
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Category: Software

Hello

1.I would like to know if the ZC706 with the ADRV9009 can support 400 MHz bandwidth on the ORx and Tx channels. I just need 1xORX and 1xTX(TX1+ORX1 400MHZbw)

2. If yes how? should we change the lane number to 2 m k l ..., change devicetree to match HDL 3.change profile?

THANKS ,Joshua

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software on Nov 11, 2025 1:04 PM
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Thanks Bianca, here is my jesdstatus however I can load RX200_Orx200_TX200 but no chance to load RX100_TX400_ORX400 I enable XCVR_QPLL for all, and it is part of kernel logs=axi_adxcvr_drv 44a60000.axi-adxcvr-rx: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
axi_adxcvr_drv 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr_drv 44a50000.axi-adxcvr-rx-os: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
axi_adxcvr_drv 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.05.a) using QPLL on GTX2 at 0x44A50000. Number of lanes: 2.
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
axi_sysid 45000000.axi-sysid-0: [adrv9009] [RX:M=4 L=2 S=1 TX:M=4 L=4 S=1 RX_OS:M=2 L=2 S=1 DAC_FIFO_ADDR_WIDTH=10] on [zc706] git branch <hdl_2023_r2> git <d146370c10fdd55156de2bafdd9b24292c01b6e1> dirty [2025-11-10 16:38:06] UTC .... do I change DT or hdl
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software on Nov 11, 2025 1:23 PM in reply to software

for extra information I use vcxo122.88 diff osc both pin connect to refA and change in DT adi,refa-enable;
        adi,refa-diff-rcv-enable;
        adi,refa-r-div = <4>;
        //adi,osc-in-cmos-neg-inp-enable;
        adi,osc-in-diff-enable; status0/spi0=0 status1/spi1=1 for div=2 both status is 1 nothing change for default DT is made also I use KERNEL_DTB="zynq-zc706-adv7511-adrv9009-jesd204-fsm"

Fullscreen kernellog.txt Download

usbcore: registered new device driver usb
mc: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-tx@44a80000
jesd204: created con: id=1, topo=0, link=2, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@44a50000
jesd204: created con: id=2, topo=0, link=1, /axi/spi@e0006000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx@44a60000
jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@44a50000 <-> /fpga-axi@0/axi-jesd204-rx-os@44ab0000
jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44a80000 <-> /fpga-axi@0/axi-jesd204-tx@44a90000
jesd204: created con: id=5, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@44a60000 <-> /fpga-axi@0/axi-jesd204-rx@44aa0000
jesd204: created con: id=6, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44a90000 <-> /fpga-axi@0/axi-adrv9009-tx-hpc@44a04000
jesd204: created con: id=7, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@44aa0000 <-> /axi/spi@e0006000/adrv9009-phy@1
jesd204: created con: id=8, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx-os@44ab0000 <-> /axi/spi@e0006000/adrv9009-phy@1
jesd204: created con: id=9, topo=0, link=0, /fpga-axi@0/axi-adrv9009-tx-hpc@44a04000 <-> /axi/spi@e0006000/adrv9009-phy@1
jesd204: /axi/spi@e0006000/adrv9009-phy@1: JESD204[0:0] transition uninitialized -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@1: JESD204[0:1] transition uninitialized -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@1: JESD204[0:2] transition uninitialized -> initialized
jesd204: found 9 devices and 1 topologies
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered PF_INET protocol family
IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear)
TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
armv7-pmu f8891000.pmu: hw perfevents: no interrupt-affinity property, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=18 bucket_order=0
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
nfs4filelayout_init: NFSv4 File Layout Driver Registering...
nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
fuse: init (API version 7.37)
bounce: pool size: 64 pages
io scheduler mq-deadline registered
io scheduler kyber registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dma-controller: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dma-controller: 	DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
Registered mathworks_ip class
SPI driver spidev has no spi_device_id for adi,swspi
MACsec IEEE 802.1AE
tun: Universal TUN/TAP device driver, 1.6
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 44 (00:0a:35:00:00:00)
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver net1080
usbcore: registered new interface driver cdc_subset
usbcore: registered new interface driver zaurus
usbcore: registered new interface driver cdc_ncm
usbcore: registered new interface driver r8153_ecm
usbcore: registered new interface driver uas
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver upd78f0730
usbserial: USB Serial support registered for upd78f0730
ci_hdrc ci_hdrc.0: unable to init phy: -110
ci_hdrc: probe of ci_hdrc.0 failed with error -110
SPI driver ads7846 has no spi_device_id for ti,tsc2046
SPI driver ads7846 has no spi_device_id for ti,ads7843
SPI driver ads7846 has no spi_device_id for ti,ads7845
SPI driver ads7846 has no spi_device_id for ti,ads7873
i2c_dev: i2c /dev entries driver
gspca_main: v2.14.0 registered
usbcore: registered new interface driver uvcvideo
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
hid: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
SPI driver fb_seps525 has no spi_device_id for syncoam,seps525
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
ad9528 spi0.0: supply vcc not found, using dummy regulator
iio iio:device1: DBG R[0000]=0 (rret=0)
iio iio:device1: DBG R[0001]=0 (rret=0)
iio iio:device1: DBG R[0002]=0 (rret=0)
iio iio:device1: DBG R[0003]=0 (rret=0)
iio iio:device1: DBG R[000F]=0 (rret=0)
mmc0: new high speed SDHC card at address aaaa
iio iio:device1: DBG R[0230]=0 (rret=0)
mmcblk0: mmc0:aaaa SD32G 29.7 GiB 
iio iio:device1: DBG CHIP_ID try=0 -> 0xFF05
 mmcblk0: p1 p2 p3
iio iio:device1: DBG PLL1: refa_en=1 refb_en=0 pll1_bypass=0 refa_diff=1 refb_diff=0
iio iio:device1: DBG setup: waiting for PLL2 calibration (IS_CALIBRATING -> 0)
iio iio:device1: DBG poll: addr=0x20509 mask=0x100 expect=0x0
iio iio:device1: DBG poll: val=0xE6 (timeout=99)
iio iio:device1: DBG sync: waiting for VCXO_OK and PLL2_LOCKED
iio iio:device1: DBG poll: addr=0x20509 mask=0x22 expect=0x22
iio iio:device1: DBG poll: val=0xE6 (timeout=99)
jesd204: /axi/spi@e0006000/ad9528-1@0,jesd204:0,parent=spi0.0: Using as SYSREF provider
SPI driver adis16475 has no spi_device_id for adi,adis16470
SPI driver adis16475 has no spi_device_id for adi,adis16475-1
SPI driver adis16475 has no spi_device_id for adi,adis16475-2
SPI driver adis16475 has no spi_device_id for adi,adis16475-3
SPI driver adis16475 has no spi_device_id for adi,adis16477-1
SPI driver adis16475 has no spi_device_id for adi,adis16477-2
SPI driver adis16475 has no spi_device_id for adi,adis16477-3
SPI driver adis16475 has no spi_device_id for adi,adis16465-1
SPI driver adis16475 has no spi_device_id for adi,adis16465-2
SPI driver adis16475 has no spi_device_id for adi,adis16465-3
SPI driver adis16475 has no spi_device_id for adi,adis16467-1
SPI driver adis16475 has no spi_device_id for adi,adis16467-2
SPI driver adis16475 has no spi_device_id for adi,adis16467-3
SPI driver adis16475 has no spi_device_id for adi,adis16500
SPI driver adis16475 has no spi_device_id for adi,adis16501
SPI driver adis16475 has no spi_device_id for adi,adis16505-1
SPI driver adis16475 has no spi_device_id for adi,adis16505-2
SPI driver adis16475 has no spi_device_id for adi,adis16505-3
SPI driver adis16475 has no spi_device_id for adi,adis16507-1
SPI driver adis16475 has no spi_device_id for adi,adis16507-2
SPI driver adis16475 has no spi_device_id for adi,adis16507-3
SPI driver adis16475 has no spi_device_id for adi,adis16575-2
SPI driver adis16475 has no spi_device_id for adi,adis16575-3
SPI driver adis16475 has no spi_device_id for adi,adis16576-2
SPI driver adis16475 has no spi_device_id for adi,adis16576-3
SPI driver adis16475 has no spi_device_id for adi,adis16577-2
SPI driver adis16475 has no spi_device_id for adi,adis16577-3
axi_adxcvr_drv 44a60000.axi-adxcvr-rx: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
axi_adxcvr_drv 44a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 2.
axi_adxcvr_drv 44a50000.axi-adxcvr-rx-os: adxcvr_enforce_settings: Using QPLL without access, assuming desired Lane rate will be configured by a different instance
axi_adxcvr_drv 44a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.05.a) using QPLL on GTX2 at 0x44A50000. Number of lanes: 2.
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A80000. Number of lanes: 4.
axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found
axi_sysid 45000000.axi-sysid-0: [adrv9009] [RX:M=4 L=2 S=1 TX:M=4 L=4 S=1 RX_OS:M=2 L=2 S=1 DAC_FIFO_ADDR_WIDTH=10] on [zc706] git branch <hdl_2023_r2> git <d146370c10fdd55156de2bafdd9b24292c01b6e1> dirty [2025-11-10 16:38:06] UTC
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
usbcore: registered new interface driver snd-usb-audio
NET: Registered PF_INET6 protocol family
Segment Routing with IPv6
In-situ OAM (IOAM) with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered PF_PACKET protocol family
NET: Registered PF_IEEE802154 protocol family
Key type dns_resolver registered
zynq_pm_remap_ocm: OCM pool is not available
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
axi-jesd204-rx 44ab0000.axi-jesd204-rx-os: AXI-JESD204-RX (1.07.a) at 0x44AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
adrv9009 spi0.1: adrv9009_probe : enter
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> initialized
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_pre_setup
iio iio:device1: DBG sync: waiting for VCXO_OK and PLL2_LOCKED
iio iio:device1: DBG poll: addr=0x20509 mask=0x22 expect=0x22
iio iio:device1: DBG poll: val=0xE6 (timeout=99)
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
adrv9009 spi0.1: ADIHAL_resetHw
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_setup -> opt_setup_stage1
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_setup -> opt_setup_stage1
random: crng init done
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clocks_enable -> link_enable
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clocks_enable -> link_enable
adrv9009 spi0.1: Link1 TAL_FRAMER_A framerStatus 0x21
adrv9009 spi0.1: Link2 TAL_FRAMER_A framerStatus 0x2F
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_enable -> link_running
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_enable -> link_running
adrv9009 spi0.1: adrv9009_info: adrv9009 Rev 192, Firmware 6.2.1 API version: 3.6.2.1 successfully initialized via jesd204-fsm
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_running -> opt_post_running_stage
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_running -> opt_post_running_stage
jesd204: /axi/spi@e0006000/adrv9009-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_running -> opt_post_running_stage
cf_axi_dds 44a04000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x44A04000 mapped to 0x66637672, probed DDS AD9371
cf_axi_adc 44a00000.axi-adrv9009-rx-hpc: ADI AIM (10.03.) at 0x44A00000 mapped to 0x63e24592 probed ADC ADRV9009 as MASTER
of_cfs_init
of_cfs_init: OK
ALSA device list:

CapotaBianca

on Nov 18, 2025 11:26 AM in reply to software
+1
Hello software,

We suggest the following modifications:

In projects/adrv9009/common/adrv9009_bd.tcl change ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080 to ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 40 https://github.com/analogdevicesinc/hdl/blob/807916e03713ea56d8c869c792fd0491a5313e1c/projects/adrv9009/common/adrv9009_bd.tcl#L235C1-L235C59 and in device tree file https://github.com/analogdevicesinc/linux/blob/42c449f029e5bf691218435ca01ce83d1a4306a5/arch/arm/boot/dts/adi-adrv9009.dtsi#L75, update adi,channel-divider = <10> with adi,channel-divider = <5> for all 4 channels.

As an alternative solution, you can adjust the interpolation filter configuration by doubling the corresponding frequency values.

https://github.com/analogdevicesinc/hdl/blob/807916e03713ea56d8c869c792fd0491a5313e1c/projects/adrv9009/common/adrv9009_bd.tcl#L91-L92 change 122.88 ->245.76 and 15.36 ->30.72.

https://github.com/analogdevicesinc/hdl/blob/807916e03713ea56d8c869c792fd0491a5313e1c/projects/adrv9009/common/adrv9009_bd.tcl#L158-L159 change 122.88 ->245.76 and 122.88 ->245.76.

After applying these changes, please let us know if you still encounter any issues.

Regards,

Bianca
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CapotaBianca

on Nov 25, 2025 6:37 AM in reply to CapotaBianca
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Hello software,

Do you have any updates on this thread?

Regards,

Bianca
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CapotaBianca

on Dec 2, 2025 6:34 AM in reply to CapotaBianca
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CapotaBianca

on Dec 2, 2025 6:34 AM in reply to CapotaBianca
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