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We have an application that is very sensitive to latency in both the TX and RX paths.

The AD9364 Reference Manual explains the latency due to the digital filters, but in addition to this latency, we are measuring an additional latency that is not explained in the data sheet or reference manual.

Our clock setup using the no-os drivers is as follows:
ad9361_set_trx_clock_chain: 960000000 480000000 240000000 120000000 60000000 60000000
ad9361_set_trx_clock_chain: 960000000 240000000 120000000 60000000 60000000 60000000

Looking at the AD9364 users guide "DIGITAL Rx BLOCK DELAY" it looks like I should be seeing a delay contribution from the digital filters of approx:
HB3           HB2           HB1
RX path (2/240M) + (2/120M) + (7/60M) = 8.3ns + 16.6ns + 116ns = 140ns
TX path (2/120M) + (2/60M)  + 0             = 16.6ns + 33.8ns             =  50.4ns

= 190.4ns total delay for digital filters

I am using an ILA (logic analyzer) in our FPGA to capture the TX and RX data just before clocking in/out to the AD9364.  I am seeing a delay of approx. 800ns.

I know that the 190ns is only the digital filter delay.  Is there a description somewhere of what the source might be for the additional ~600ns delay I am measuring?

Most importantly for our application, is there anything that can be done to reduce the latency below the 800ns we are currently seeing?

Thank you for any assistance.

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• Following are register values actually read from device at run time.
register[0x2]=0x58
register[0x3]=0x5c

So for TX filters (register 0x2) this is:
D6 = 1 : TX channel enabled
D5:4 = 01 : HB3 enabled with interpolate by 2
D3 = 1 : HB2 enabled interpolate by 2
D2 = 0 : HB1 bypassed interpolate by 1
D1:0 = 00 : FIR filter bypassed interpolate by 1

For RX filters (register 0x3) this is:
D6 = 1 : RX channel enabled
D5:4 = 01 : HB3 enabled with decimate by 2
D3 = 1 : HB2 enabled decimate by 2
D2 = 1 : HB1 enabled decimate by 2
D1:0 = 00 : FIR bypassed decimate by 1

Just to be sure that the FIRs are configured as expected, I also intentionally enabled the RX and TX FIR with 16 taps each and saw a correpsonding increase in latency so I am very certain the FIRs are being bypassed as expected.

I am confused by the RX path delay calculation you show. Shouldn't it be the output clock rate from each filter that is used (after decimate)? That's what the datasheet shows. It looks like you are using the input filter rate (before decimate). In any case, I made the same mistake for the TX path I show in the original post so the delay should be even less than I show.

So I think what it should be is :

 Filter TX clock Interpolation Filter order Delay RX clock Decimation Filter order FIR 6.00E+07 1 37 0.00E+00 6.00E+07 1 37 0.00E+00 HB1 6.00E+07 1 0 0.00E+00 1.20E+08 2 14 1.17E-07 HB2 1.20E+08 2 6 2.50E-08 2.40E+08 2 6 2.50E-08 HB3 2.40E+08 2 4 8.33E-09 4.80E+08 2 4 8.33E-09 TX Delay 3.33E-08 RX delay 1.50E-07

This gives a grand total of 183ns, which is a bit less than I originally calculated.

As mentioned.  I don't have Matlab so can't run the filter wizard.  What does it show the latency should be including the analog filters?

In our actual system, I am using a QPSK pi/4 modulator/demodulator in our baseband processor (FPGA).  I am instantiating an ILA in Vivado to capture the baseband data just as it is being received / transmitted  to/from the FPGA using an LVDS interface.  This is using the Analog Devices HDL reference AD9361 HDL Reference Designs [Analog Devices Wiki] axi_ad9361_lvds_if.v and the ILA is connected to this modules adc_data and dac_data nets.  The ILA is capturing the data signals using the AD9361 rx clock domain (120MHz in this case because of the lvds interface).

To test I am setting both RX and TX LO to the same frequency and sending some number of 00 symbols (45degree phase shift per symbol because of the PI/4) then sending a 01 symbol and watching the phase change propogate out the TX path and then being received in the RX path.

So the question is are there expected delays in addition to the filters that would explain the total latency I am seeing of approx. 800ns (approx. 600ns still unaccounted for)?

Thanks for any assistance.

• Following are register values actually read from device at run time.
register[0x2]=0x58
register[0x3]=0x5c

So for TX filters (register 0x2) this is:
D6 = 1 : TX channel enabled
D5:4 = 01 : HB3 enabled with interpolate by 2
D3 = 1 : HB2 enabled interpolate by 2
D2 = 0 : HB1 bypassed interpolate by 1
D1:0 = 00 : FIR filter bypassed interpolate by 1

For RX filters (register 0x3) this is:
D6 = 1 : RX channel enabled
D5:4 = 01 : HB3 enabled with decimate by 2
D3 = 1 : HB2 enabled decimate by 2
D2 = 1 : HB1 enabled decimate by 2
D1:0 = 00 : FIR bypassed decimate by 1

Just to be sure that the FIRs are configured as expected, I also intentionally enabled the RX and TX FIR with 16 taps each and saw a correpsonding increase in latency so I am very certain the FIRs are being bypassed as expected.

I am confused by the RX path delay calculation you show. Shouldn't it be the output clock rate from each filter that is used (after decimate)? That's what the datasheet shows. It looks like you are using the input filter rate (before decimate). In any case, I made the same mistake for the TX path I show in the original post so the delay should be even less than I show.

So I think what it should be is :

 Filter TX clock Interpolation Filter order Delay RX clock Decimation Filter order FIR 6.00E+07 1 37 0.00E+00 6.00E+07 1 37 0.00E+00 HB1 6.00E+07 1 0 0.00E+00 1.20E+08 2 14 1.17E-07 HB2 1.20E+08 2 6 2.50E-08 2.40E+08 2 6 2.50E-08 HB3 2.40E+08 2 4 8.33E-09 4.80E+08 2 4 8.33E-09 TX Delay 3.33E-08 RX delay 1.50E-07

This gives a grand total of 183ns, which is a bit less than I originally calculated.

As mentioned.  I don't have Matlab so can't run the filter wizard.  What does it show the latency should be including the analog filters?

In our actual system, I am using a QPSK pi/4 modulator/demodulator in our baseband processor (FPGA).  I am instantiating an ILA in Vivado to capture the baseband data just as it is being received / transmitted  to/from the FPGA using an LVDS interface.  This is using the Analog Devices HDL reference AD9361 HDL Reference Designs [Analog Devices Wiki] axi_ad9361_lvds_if.v and the ILA is connected to this modules adc_data and dac_data nets.  The ILA is capturing the data signals using the AD9361 rx clock domain (120MHz in this case because of the lvds interface).

To test I am setting both RX and TX LO to the same frequency and sending some number of 00 symbols (45degree phase shift per symbol because of the PI/4) then sending a 01 symbol and watching the phase change propogate out the TX path and then being received in the RX path.

So the question is are there expected delays in addition to the filters that would explain the total latency I am seeing of approx. 800ns (approx. 600ns still unaccounted for)?

Thanks for any assistance.

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