AD9361 FAST AGC

Which standard are you working with?

Do you have a timing specification you are trying to achieve for AGC convergence? How much of an improvement are you looking for?

What hardware are you using and how are you configuring the part?

We are using an LTE like system

The guard interval time is about 5.7usec, I would like convergence within 2-3usec.

We are using our own HW.

The System is using the No-OS driver and is configuring it the following:

    phy->pdata->gain_ctrl.adc_large_overload_exceed_counter = 10;

    phy->pdata->gain_ctrl.adc_large_overload_inc_steps = 5;

    phy->pdata->gain_ctrl.adc_lmt_small_overload_prevent_gain_inc = FALSE;

    phy->pdata->gain_ctrl.adc_small_overload_exceed_counter = 10;

    phy->pdata->gain_ctrl.adc_small_overload_inc_steps = 4;

    phy->pdata->gain_ctrl.dig_gain_step_size = 4;

    phy->pdata->gain_ctrl.dig_saturation_exceed_counter = 3;

    phy->pdata->gain_ctrl.gain_update_interval_us = 1000;

    phy->pdata->gain_ctrl.immed_gain_change_if_large_adc_overload = FALSE;

    phy->pdata->gain_ctrl.immed_gain_change_if_large_lmt_overload = FALSE;

    phy->pdata->gain_ctrl.agc_inner_thresh_high = 10;

    phy->pdata->gain_ctrl.agc_inner_thresh_high_dec_steps = 1;

    phy->pdata->gain_ctrl.agc_inner_thresh_low = 12;

    phy->pdata->gain_ctrl.agc_inner_thresh_low_inc_steps = 1;

    phy->pdata->gain_ctrl.lmt_overload_large_exceed_counter = 10;

    phy->pdata->gain_ctrl.lmt_overload_large_inc_steps = 2;

    phy->pdata->gain_ctrl.lmt_overload_small_exceed_counter = 10;

    phy->pdata->gain_ctrl.agc_outer_thresh_high = 5;

    phy->pdata->gain_ctrl.agc_outer_thresh_high_dec_steps = 2;

    phy->pdata->gain_ctrl.agc_outer_thresh_low = 18;

    phy->pdata->gain_ctrl.agc_outer_thresh_low_inc_steps = 2;

    phy->pdata->gain_ctrl.agc_attack_delay_extra_margin_us = 2;

    phy->pdata->gain_ctrl.sync_for_gain_counter_en = FALSE;

The system is a TDD one, where we use the chip in TDD mode (and not FDD).

Thanks,

It will be hard to meet 2-3us convergence or lock time.

I would recommend using Fast Lock AGC algorithm. The function calls you provided appear to be for slow AGC.

The way to come close to meeting your specification is to run the part at maximum output data rate which in turn will maximize ClkRF at 122.88MHz. AGC is clocked by ClkRF and the faster ClkRF the faster the AGC operates.