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AD9361 Wide Bandwidth Noise Floor Shape Issue

We have designed a circuit board with the AD9361 and see some unexpected noise floor shapes when receiving 54 MHz of bandwidth through the chip. All of the bandwidths were created using the Matlab AD9361 plug-in. Attached are two spectral views. The first uses a 40 MHz bandwidth and shows a reasonably flat noise floor. The second view uses the 54 MHz filter but the noise floor at each end rises up about 10 dB then starts to tail off. The noise floor on the transmit output for both the 40 MHz and 54 MHz bandwidth are flat.


Are these noise floor lobes due to the sigma-delta ADC? Is there some way to get rid of or reduce them? The 54 MHz bandwidth uses an ADC rate of 480 MHz and a final sample rate of 60 MHz (decimate by 8). We can't run the ADC at a higher rate without violating the max transfer rate between the AD9361 and our FPGA since we use FDD mode and all channels (RX1, RX2, TX1 and TX2).


  • It could be the filter response that you are seeing. Can you remove the input Rx signal, terminate the input and run it at max gain? This experiment should show the filter response and once it does you can try to correlate it with the shape you are seeing now.

    I don't think it is the sigma delta ADC since you are running it a much greater rate than your bandwidth of interest. Sigma delta ADC does have noise transfer function that increases with frequency.


    Attached is a set of plots that show the affect of gain on the noise floor with no input signal. It appears the amplifier noise overcomes the noise lobes once the gain gets high enough. How do we flatten the noise floor for smaller gain values?

    I have attached a second plot that shows the affect of gain on the noise floor for a 36 MHz bandwidth. The initial plot was for a 54 MHz bandwidth. Notice that the 36 MHz noise floor is flat for all gain levels unlike the 54 MHz plots which show the noise lobes towards each end of the band for lower gain values. The 54 MHz bandwidth runs the ADC at 480 MHz and decimates by 8 for a complex output sample rate of 60 Msps. The 36 MHz filter runs the ADC at 640 MHz and decimates by 16 to yield a complex output sample rate of 40 Msps. The fact that the 36 MHz plots look much better than the 54 MHz plots and that it uses a higher ADC rate led us to wonder if the noise lobes for the 54 MHz plots are due to ADC response even though your response was leaning towards the analog filter setup.

    Please advise us on how we can improve the 54 MHz response.



  • Is your filter for 56MHz tuned to max bandwidth? Max bandwidth of the analog filter is 28MHz 3dB cutoff frequency, so the filter starts to roll off before that point. If you are using emphasis for amplitude magnitude equalization in the digital filter you will most likely see peaking in the noise response.

    Are you doing amplitude magnitude equalization?

  • We are tuned to the max bandwidth and we are not using amplitude emphasis. Attached are charts showing the filter response from the Analog Devices filter design tool for Matlab. The Rx and Tx paths are included for completeness.

  • The noise floor shaping is due to the ADC noise shaping. Running the ADC at a higher sampling rate can help improve noise floor flatness.

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