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AD9364 Reference Clock Requirements

Thread Summary

The user inquired about the valid input frequency range for the external reference clock of the AD9361/AD9364 transceiver, specifically whether a 125 MHz TCXO is suitable. The final answer confirmed that the AD9364 can accept an external reference clock from 5 MHz to 320 MHz, with internal dividers/multipliers ensuring the PLL phase detector operates within 10 MHz to 80 MHz. A 125 MHz external reference is valid and should be checked for frequency planning to meet the design requirements.
AI Generated Content
Category: Hardware
Product Number: AD9364

Hi,

I am designing a transceiver with a RX band of 2.025 - 2.110 GHz and a TX band of 2.200 - 2.290 GHz. I was hoping to use a 125 MHz TCXO in this design, avoiding any harmonics in the RX band (with a single even harmonic in the TX band).
However, after doing some reading, I've found this forum discussion (AD9361- Asynchronous Behavior between DATA_CLK and the reference clock (XTAL_IN)? Could you help me to understand where is the problem and how to resolve it please?), indicating that the reference manual is not accurate and that the range is 10 - 80 MHz. However, the reference manual has not been updated and still states that the input range is 5 - 320 MHz, which can then be prescaled.

Could you please confirm which is true?

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