Post Go back to editing

Failure to tune sampling clock at cold temperatures and higher sample rates

Category: Hardware
Product Number: AD9364

Hello,

We have been using the AD9364 for a number of years in a design based on the FMCOMMS board. Recently, we noticed that some units fail to lock at cold temperatures. I've boiled the problem down to a fairly simple set of steps:

1. Initial part with the ADI  IIO driver.

2. Attempt to set the sampling frequency by using the command line interface:

echo 61440000 > /sys/devices/soc0/axi/e0006000.spi/spi_master/spi1/spi1.0/iio:device0/in_voltage_sampling_frequency

3. Check the error messages via dmesg, which reports the following:

ad9361 spi1.0: ad9361_dig_tune_delay: Tuning RX FAILED!
SAMPL CLK: 61440000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
When this error occurs we do not get samples that we request over the IIO interface.
This made no difference that I can see. We are able to tune lower frequencies (below 57 MHz), but anything above that causes the error.
What else can I look at to figure out why we are having this issue? Some units do not appear to have the problem at all, but some consistently fail to tune the sampling clock.
-Dave

 

Parents
  • I've run the timing analysis at various temperatures and attached the full log. The most interesting results are from testing at -20 C. I will paste a subset of the results at the end of the message. I am unable to probe DATA_CLK and RX_FRAME because the traces are buried underneath the parts and on inner layers of the PCB.

    Seeing that the timing analysis fails, is there any adjustment I can do in the FPGA to compensate?

    -Dave

    Timing Analysis Results at -20 C
    ========================================================================

    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 20479999 > /sys/bus/iio/devices/iio:device0/in_voltage_sampling_frequency 
    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 1 > bist_timing_analysis 
    root@localhost:/sys/kernel/debug/iio/iio:device0# cat bist_timing_analysis 
    CLK: 20479999 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:o o o o o . . . . . . . . . . . 
    1:o o o o o o . . . . . . . . . . 
    2:o o o o o o o . . . . . . . . . 
    3:o o o o o o o o . . . . . . . . 
    4:o o o o o o o o o . . . . . . . 
    5:o o o o o o o o o o . . . . . . 
    6:o o o o o o o o o o o . . . . . 
    7:o o o o o o o o o o o o . . . . 
    8:o o o o o o o o o o o o o . . . 
    9:o o o o o o o o o o o o o o . . 
    a:o o o o o o o o o o o o o o o . 
    b:o o o o o o o o o o o o o o o o 
    c:o o o o o o o o o o o o o o o o 
    d:o o o o o o o o o o o o o o o o 
    e:o o o o o o o o o o o o o o o o 
    f:o o o o o o o o o o o o o o o o 

    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 61440000 > /sys/bus/iio/devices/iio:device0/in_voltage_sampling_frequency 
    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 1 > bist_timing_analysis 
    root@localhost:/sys/kernel/debug/iio/iio:device0# cat bist_timing_analysis 
    CLK: 61440000 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:. . . . . . . . . . . . . . . . 
    1:. . . . . . . . . . . . . . . . 
    2:. . . . . . . . . . . . . . . . 
    3:. . . . . . . . . . . . . . . . 
    4:. . . . . . . . . . . . . . . . 
    5:. . . . . . . . . . . . . . . . 
    6:. . . . . . . . . . . . . . . . 
    7:. . . . . . . . . . . . . . . . 
    8:. . . . . . . . . . . . . . . . 
    9:. . . . . . . . . . . . . . . . 
    a:. . . . . . . . . . . . . . . . 
    b:. . . . . . . . . . . . . . . . 
    c:. . . . . . . . . . . . . . . . 
    d:. . . . . . . . . . . . . . . . 
    e:. . . . . . . . . . . . . . . . 
    f:. . . . . . . . . . . . . . . . 

    ad9361 spi1.0: ad9361_dig_tune_delay: Tuning RX FAILED!


    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 60000000 > /sys/bus/iio/devices/iio:device0/in_voltage_sampling_frequency 
    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 1 > bist_timing_analysis 
    root@localhost:/sys/kernel/debug/iio/iio:device0# cat bist_timing_analysis 
    CLK: 60000000 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:. . . . . . . . . . . . . . . . 
    1:. . . . . . . . . . . . . . . . 
    2:. . . . . . . . . . . . . . . . 
    3:. . . . . . . . . . . . . . . . 
    4:. . . . . . . . . . . . . . . . 
    5:. . . . . . . . . . . . . . . . 
    6:. . . . . . . . . . . . . . . . 
    7:. . . . . . . . . . . . . . . . 
    8:. . o . . . . . . . . . . . . . 
    9:. . . . . . . . . . . . . . . . 
    a:. . . . o . . . . . . . . . . . 
    b:. . . . . . . . . . . . . . . . 
    c:. . . . . . . . . . . . . . . . 
    d:. . . . . . . . . . . . . . . . 
    e:. . . . . . . . . . . . . . . . 
    f:. . . . . . . . . . . . . . . .
    root@localhost:/sys/kernel/debug/iio/iio:device0# 

    root@localhost:/sys/kernel/debug/iio/iio:device0# dmesg 
    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 59000000 > /sys/bus/iio/devices/iio:device0/in_voltage_sampling_frequency 
    root@localhost:/sys/kernel/debug/iio/iio:device0# echo 1 > bist_timing_analysis 
    root@localhost:/sys/kernel/debug/iio/iio:device0# cat bist_timing_analysis 
    CLK: 59000000 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:. . . . . . . . . . . . . . . . 
    1:. . . . . . . . . . . . . . . . 
    2:. . . . . . . . . . . . . . . . 
    3:. . . . . . . . . . . . . . . . 
    4:. . . . . . . . . . . . . . . . 
    5:o . . . . . . . . . . . . . . . 
    6:. o . . . . . . . . . . . . . . 
    7:o o . . . . . . . . . . . . . . 
    8:. o . . . . . . . . . . . . . . 
    9:. . o . . . . . . . . . . . . . 
    a:. . . o o . . . . . . . . . . . 
    b:. . . o o o . . . . . . . . . . 
    c:. . . . o o . . . . . . . . . . 
    d:. . . . . o . . . . . . . . . . 
    e:. . . . . . o . . . . . . . . . 
    f:. . . . . . o o o . . . . . . . 

  • HI  ,

    Looks like this board's signal integrity on LVDS signals is poor at lower temperatures. Please can you check the same behavior on working boards to get the better clarity.

    Also, can you provide the LVDS configuration details to check.

    Regards,

    SJ

Reply Children

Before You Switch


Switching languages will make ADI Explorer unavailable. Resume your session by switching back to English and reopening ADI Explorer.