Max streaming capability over UDP

Hi ortigoza ,

Which is the resource consumption on the CPU subsystem from your FPGA SoC? When you try to stream data at max. rate

reported from > top:

while idle 1% CPU  1.5% memory accross some processes

running the python UDP stream:

  PID USER      PR  NI    VIRT    RES    SHR S            %CPU        %MEM     TIME+ COMMAND

1277   root       20    0 172824 52060     23104 R          100.0           5.1          0:37.01 python
1282   root       20    0 147236 34188     12964 R          46.9             3.4          0:15.61 python

%Cpu(s): 49.7 us, 24.6 sy, 0.0 ni, 25.7 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
MiB Mem : 990.3 total, 480.7 free, 222.5 used, 287.0 buff/cache
MiB Swap: 100.0 total, 100.0 free, 0.0 used. 674.6 avail Mem

I would also like to point out that I made a modified version of the UDP stream to sample at 11Msps (sub the theoretical max) and the processor time is able to follow the live streaming time. (meaning no gaps in the data)

Ok, yes, in this case of having an under 1 Gb transmission, the small sys_ps7 subsystem from the SoC should be able to perform a near line-rate reception and then transmission using RAM, even if there would be two mem-related operations made in this process, one . The best and simplified methodology for this data transmission over Ethernet would be to create the UDP/IPv4/Ethernet packets in HW and then transmit them using an attached 1Gb-capable Ethernet PHY, but this would be require the use of FPGA-attached PHYs (by Xilinx or ADI's CN0506 connected through the FMC connector).

Are you saying that I would need to modify the zynq hardware design and create a UDP packetizer?

I was hoping to be able to accomplish something with the current hardware/softare ecosystem

Hi,

We don't have specific measurements for this converter data transmission setup over 1Gb Ethernet (related to the max. rate that can be supported with this two DMA-based operations and various CPU subsystems configurations - for data capture and then data transmission over network). In this case, using a small 2 core-based CPU subsystem for this 2 mem-based operations seems to be insufficient to carry on a near line rate transmission even if one core is at only ~50%. Do you use jumbo frames setup? (using an MTU of 9000 for example). To implement both FPGA-based data reception and network transmission, another hardware setup would be needed in order to have both convertor and Ethernet PHY connected to the FPGA region.

Best regards,

Alin 

Hi ortigoza !

Were all your questions answered, or is there anything else we can help with?

Regards, Elena

Yes, it appears my question has been answered as far as max rate capability with the default Hardware/Software ecosystem you provide. 

A custom hardware design would need to be implemented in the PL that packetizes data directly off of the ADC, which unfortunately will go beyond the scope of my quick approach.

Yes, it appears my question has been answered as far as max rate capability with the default Hardware/Software ecosystem you provide. 

A custom hardware design would need to be implemented in the PL that packetizes data directly off of the ADC, which unfortunately will go beyond the scope of my quick approach.