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Why does the RSSI value stay fixed and wrong when the sampling rate is low?

Category: Software
Product Number: AD9361S

I'm using the AD9361 to get the RSSI value, with a bandwidth of 200K and an LO of 1G, for slow attack AGC. When I set the sampling rate to 8.3MHz or higher, I get the correct RSSI value, but if I set the sampling rate to 8.2MHz or lower, the RSSI value stays fixed and is wrong. Do you know why this happens?The RSSI register is set as follows:                   
ad9361_spi_write(spi,0x150,0x0b);
ad9361_spi_write(spi,0x151,0);
ad9361_spi_write(spi,0x152,0xff);
ad9361_spi_write(spi,0x153,0);
ad9361_spi_write(spi,0x154,0);
ad9361_spi_write(spi,0x155,0);
ad9361_spi_write(spi,0x156,0);
ad9361_spi_write(spi,0x157,0);
ad9361_spi_write(spi,0x158,0x0d); // AGC gain change
ad9361_spi_write(spi,0x15c,0x69);

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  • HI  

    We would request to first monitor - Current gain index, RSSI value, AGC gain-update events at: 8.3 MHz and 8.2 MHz

    If the gain index becomes fixed at 8.2 MHz, then the RSSI accumulator may never be restarting in the way you expect.

    If you are using a custom FIR filter, verify that it was generated for both sample rates. An invalid filter/clock configuration can cause unexpected behavior in RSSI, AGC, and power measurements. 
    with the configuration change it suggests a clock-chain/filter-mode transition in the AD9361. 
    Regards,

    SJ

Reply
  • HI  

    We would request to first monitor - Current gain index, RSSI value, AGC gain-update events at: 8.3 MHz and 8.2 MHz

    If the gain index becomes fixed at 8.2 MHz, then the RSSI accumulator may never be restarting in the way you expect.

    If you are using a custom FIR filter, verify that it was generated for both sample rates. An invalid filter/clock configuration can cause unexpected behavior in RSSI, AGC, and power measurements. 
    with the configuration change it suggests a clock-chain/filter-mode transition in the AD9361. 
    Regards,

    SJ

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