How to Transfer AD9361 RF DMA Data to/from PL-DDR in FMCOMMS5-Based Design

Hi ADI Team,

I am using the FMCOMMS5 reference design.

In the reference design, the ADC DMA and DAC DMA are mapped to PS-DDR. My requirement is to communicate RF DMA data with PL-DDR instead of PS-DDR.

Could you please provide guidance on the following?

1. What modifications are required to make the following paths work with PL-DDR?
2. Is there any reference design, example project, or documentation available that demonstrates RF DMA communication with PL-DDR?
3. Are there any limitations or requirements regarding:
   • PL-DDR size
   • AXI address mapping
   • DMA data width and burst configuration
   • Memory controller (MIG DDR4) configuration
4. Has this architecture been validated before, and is RF DMA  PL-DDR communication officially supported within the ADI HDL framework?

Currently, I can observe DMA activity, but I would like to understand the recommended approach for storing and reading RF data directly from PL-DDR.

Additionally, has ADI validated any design where AXI DMAC transfers data directly between AD9361 data paths and a PL-side DDR (MIG DDR4) instead of PS-DDR? If so, could you please share any reference design, documentation, or implementation details?

Thank you for your support.

Regards,
Sasi