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VDD_INTERFACE drawing power exponentially

Category: Hardware
Product Number: AD9364

Hi, 

I have a weird power consumption issue on the VDD_INTERFACE pin of my AD9364. 
My power supply circuit is the following :

  • LM2717 : 3V3 on fixed output = VDD_GPO 
  • LM2717 :1V8 on adj output = VDD_INTERFACE 
  • LT1962-ADJ taking VIN from LM2717 ajd output and supplying the 1V3 Anolog supply to the Rx and Tx side of AD9364. 

This was my configuration and working well for months. Then I switch the adjustable output of LM2717 to be 2V5 and have VDD_INTERFACE at 2V5 in CMOS mode. 

The probleme is that the main power supply started to draw courant exponnentially.

  1. I tried on another board and same issue.
  2. I switch back to 1V8 and same issue occured on both board.
  3. Then I isolated the VDD_INTERFACE so only H12 and LT1962 ( supplying 1V3 to Rx side (the only part that I cannot isolate)) are connected to it, and I supplied with external source: same issue on both board and on 1V8 and 2V5 supply.
  4. I tested out my LT1962 on bread board and change it, it is not the cause of the issue.
  5. I put the first PCB back in the orginal configuration ie : L2717 (3V3, 1V8) + LT1962 (Vin=1V8 -> Vout=1V3) and it worked perfectly. 
  6. I put the second PCB back in the wanted configuration  (without the isolation of VD_INTERFACE) ie : L2717 (3V3, 2V5) + LT1962 (Vin=2V5 -> Vout=1V3) and the probleme is still present 

There is no power up sequence in the documentation, I'm using the same cascaded regulator architecture than yours, what could be the issue ?  I there a power up sequence not documented ? 

Putting it back in the original configuration solved the probleme so I no composant are damaged ... So I really don't understand  

Regards 

Edit Notes

Editing as I continue to run some test, but I don't relly know what to test anymore
[edited by: Orobin at 12:26 PM (GMT -4) on 1 Apr 2026]
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  • HI  

    The AD9364 IOs are not 5V tolerant. Any external FPGA / MCU / level shifter driving the pins must also be powered from the SAME rail. If your FPGA or other digital device was still outputting 1.8 V or 3.3 V logic when you increased VDD_INTERFACE to 2.5 V, then current could enter through ESD diodes.
    If any IO pin saw a higher voltage than VDD_INTERFACE by even ~0.3 V, permanent damage is possible.
    Looks like damage occurred on AD9361 interface pins with different voltage level applied and has increased power consumption. 
    Pls check if you replace device and operate at 1.8V and still face same issue.
    Regards,
    SJ 
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