Finding out AXI DAC CHAN_CNTRLn_7 Register address for getting DMA data using DAC_DDS_SEL

hi @andrei_g 

I working with the ADRV9364Z7020 board and its reference design.
In the current reference design, I am trying to connect my custom CW signal generator inside the HDL and route it to the DAC FIFO. However, on the TX channel, I am not observing the output from my CW generator. Instead, the default DDS-generated signal is still coming out, as configured in the reference design.

I have already:
1)Added my CW signal generator module inside the HDL
2)Connected its output to the DAC FIFO path
3)Verified the CW generator logic internally in simulation

I'm stuck at finding out the AXI DAC CHAN_CNTRLn_7 Register address to write the DAC_DDS_SEL value into that register, So that I can get the CW tone through AXI DMA instead of DDS.

I have referred this thread,
FPGA Reference Design

Could you please help me out finding the Correct address for the same channels and base addresses in the mentioned thread.

Thanks and regards,