Building a design based on the ADRV9361z7035 reference design. as the simulink content grows the FPGA build fails timing. On inspection in Vivado the internal path requirement for the Simulink block is 8ns from the external pin constraint of 4ns create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] in hdl\vendor\AnalogDevices\vivado\projects\adrv9361z7035\common\adrv9361z7035_constr_lvds.xdc.
The maximum clock rate from the AD9361 from the Linux driver is 61.44MHz = 16.3ns
Setting the external pin constraint to 8ns has been tried, but it is hard to know if they may cause timing problems elsewhere in the FPGA?
It is notable that there is a divide by 2 and divide by 4 clock select in the design.
Do you have a recommended way to set the constrains while maintianing the transciever toolbox tool chain?
Timing result:
The net that is constrained to 8ns rather than 16ns:
