Constraint for internal clock using Matlab Transceiver Toolbox

moving this forum to FPGA to help further

Applied the following fix to HDL/hdl_prj/vivado_ip_prj/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc

# clocks

create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]

# Internal divide-by-4 clock, 16 ns period
create_generated_clock -name rx_clk_div4 \
-source [get_ports rx_clk_in_p] \
-divide_by 4 \
[get_pins {i_system_wrapper/system_i/util_ad9361_divclk/inst/clk_divide_sel_1/O}]

This meets timing and gives a 16ns constraint to the Simulink block.
Please confirm that this is OK.
If it is please apply it or similar to the source project.

(This ticket does not appear to have moved catorgory and it is not clear how to do so.)

Hi JohnLLA ,

Before doing any HDL changes, have you tried using the Transceiver Toolbox adrv9361z7035 example as is? It would be helpful for us to understand the way you build the design and if you added any extra logic or used a provided example. Can you elaborate a bit?

Kind regards,

Stanca

This is the Analog Devices, Inc Transceiver Toolbox verions 21.1.1 by Travis Collins, not otherwise modified in this area.
We have added an I2C interface and debug pins but this otherwise is the released code.
The timing constraint applies to the Analog Devices code.
In the diagram below you will recognise the verilog blocks in the tool box. Vivado is not aware that (presumably) the Linux driver controls d_data_cntrl_int[3]_i_1 via AXI to ensure that the maximum clock rate at clk_out is less than equal to 61.44MHz. Vivado assumes it can be 125MHz.

The above does seem to work but produces the warning:

The build process is the standard one from https://wiki.analog.com/resources/tools-software/transceiver-toolbox
There are no modifications in the verilog associated with the LVDS or other connections to the AD9361. The vast majority of the changes are within the Simulink environment.
The build process uses the Matlab Simulink HDL coder Workflow advisor, adi_build.tcl

Kind Regards

John

The external clocks that come from the AD9361 are by default 4x Datarate for LVDS. So the top-level constraint is correct.

Do you want to reduce this constraint and operate the transceiver at a lower rate?

-Travis

Hi Travis,
No 4x division is what it is using, however the toolbox is generating this block:

Which is telling Vivado that the Simulink logic must run at 4ns x 2 = 8ns rather than the actual 16ns, so 4x as you say.
clk_sel as I said above is I coming from a ADI toolbox block and so probably controlled by software so Vivado does not know that the timing of clk_out is 16ns.

Kind regards

John