I would like to clear this issue that I have with AD9361 and BIST IQ masking.
In picture AD9361_ip_connect_block_diagram.png is block diagram with AD9361 IP core IQ data port adc_data_i0/adc_data_i1 and adc_data_q0/adc_data_q1 connections. In picture VHDL_signal_connection.png is how this ports from AD9361 are connected to internal signals that are then captured with ChipScope.
In picture UG_BIST_regmap.png the UG-671 AD9361 registers for BIST are described.
Pictures CS_mask_C1-I.png shows ChipScope captured signals if C1-I is masked and picture IIO_mask_C1-I.png shows corresponding content of BIST registers when C1-I is checked in IIO Oscillosope.
Pictures CS_mask_C1-Q.png and IIO_mask_C1-Q.png shows the result if BIST C1-Q is masked.
Pictures CS_mask_C1-Q_C2-Q.png and IIO_mask_C1-Q_C2-Q.png shows result if Q is masked on both ports.
What I see is that if C1/2-I is masked, the data that comes out from AD9361 from port adc_data_q0/adc_data_q1 are masked out (zero value). Same swapping is for C1/2-Q data masking, AD9361 port adc_data_i0/adc_data_i1 are masked out (zero value).
I did this test to exclude that real signal IQ data are swapped somewhere in data path up to PC capturing:
If I output a fixed Bist TONE (no IQ masking) and than plot captured IQ data, the captured data is cos/sin plot where I data are leading Q data for 90deg. Additionally the FFT plot of this data shows tone peak frequency on the positive side (+Fs/2) of FFT plot.
Based on this plotting data I assume that AD9361 data on port adc_data_i0/adc_data_i1 are really I data and adc_data_q0/adc_data_q1 are really Q data of captured tone signal.
If this IQ data would be swapped somewhere in data pipeline, the FFT plot would result with tone peak frequency on the left side (negative side -F2/2).
From above it looks to me that register map description for BIST register 0x3F6 is not correct.
Can someone please help me out from this confusion.
WBR Primoz
