Products Mentioned

AD9361 Recommended for New Designs
The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and 4G base station applications....
Datasheet
AD9361 on Analog.com

Thread Details

  • State Not Answered
  • Replies 8 replies
  • Subscribers 50 subscribers
  • Views 401 views
  • Users 0 members are here
Options
 
Related Content

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
AD9361 Chip initialization issue in 2025.1 version

		
	
				

			

									
					    Subashini
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 22, 2026 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  AD9361  
    
    		        		        		        
    Software Version: 2025.1
    
    		    		    
    
		    		    
		    			
    
			    
    Hi Team,
    

    

    

    

    

    

    

    

    We have successfully validated the AD-FMCOMMS3-EBZ (AD9361) on the Versal device using the 2024.1 version source and FPGA design.
    

    We ported the same design to the 25.1 version and are using the 25.1 source provided by Analog Devices. However, we are encountering the error:
    

    “Unsupported Product ID 0x0.”
    

     

    We have probed the RESET and CLK signals, and both are functioning properly.
    

    Could you please guide us on how to resolve this issue?
    

    

    

    

    

    

    

    

    Thanks and Regards,
    Subashini
    
			
    
			
									
		                             
                        

    
    
                                            
                 software
                
                                                    
                 unsupported product ID
                
                                                    
                 2025.1
                
                                                    
                 ad9361
                
                                                    
                 Wideband Transceiver IC
                
                                        
                                            
                
                
                                
                    Show More
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



Parents
	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 26, 2026 3:22 AM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      HI  
      

      

      

      After one 24‑bit frame the clock stops and both MISO/MOSI go low strongly points to a bus/IO configuration issue or the chip being held in reset/powerdown/IO-level mismatch.

      

      

      

      New Vivado versions often: 
      

        

      • regenerate top‑level ports
        • 

      • reset pin directions
        • 

      • change default IOSTANDARD to LVCMOS33
         (dangerous if AD9361 is operating at 1.8 V)
        • 

      • break in/out ports if they were incorrectly declared
        • 

      • change synthesis behavior for tri‑states
        • 

      

      This directly explains why MISO/MOSI go low after 24 SPI clocks.
      

      
Recommendation would be ADI HDL uses board‑agnostic tcl scripts (system_project.tcl, fmcomms2.tcl, etc.)
      

      

      

      

      After migrating Vivado, Pls do the following:
      

       1) Pls completely regenerate the block design
       2) Pls must not reuse the old BD file
       3) Pls must rerun the ADI scripts for your platform
      

      

      

      

      Regards,
      

      SJ
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Mar 1, 2026 11:08 PM
            
            
												
						in reply to SJagini
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hi  

        Thank you for your response.
        

        As per your suggestions, we regenerated the design and also compiled the ZCU102 design from the HDL provided by Analog Devices. We then converted it to our Versal device. However, after one 24-bit SPI clock cycle, the clock, MOSI, and MISO lines are going low.
        

        In the Logic Analyzer, we are observing 0x5 on the MISO line, but when we add debug prints inside the  ad9361_spi_check function, we are getting 0x0 only.

         
         

        Thanks and Regards,
        Subashini
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Mar 3, 2026 4:48 AM
            
            
												
						in reply to Subashini
					
										
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Hi  

          The AD9361 chip initialization issue was resolved by referring to AMD's workaround.

          https://adaptivesupport.amd.com/s/article/000037096?language=en_US

          Thanks and Regards,
          Subashini
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	
        



Reply



Children
	
        No Data
        

		
			
        

        





		
        
		
        
			
          
				
        • 
					
												
						
						
						
						
						
						
						

																										
						
						

					
					
					
				
          •