AD9361 Chip initialization issue in 2025.1 version

HI Subashini 

Please check the earlier thread which has similar issue. Pls find below
(7) AD9361 Initialization Error - Unsupported PRODUCT_ID 0xFF - Q&A - Support AD9361/AD9363/AD9364 - EngineerZone

Regards,

SJ

Hi SJagini 

We have probed the XTALP/XTALN (40 MHz) on the AD-FMCOMMS3-EBZ (AD9361), but the clock is not generating in the 25.1 version.

Could you please let us know how to resolve this issue and make it work?

Thanks and Regards,
Subashini

HI Subashini 

Pls check on power supply lines to the Device and please check on the RESET pin if it is initialized properly or not. 

Typically, most of the time some pin-mapping issues on the hardware with respect to the version.

Regards,

SJ

Hi SJagini 

We have probed all the power rails and the RESET pin, and everything appears to be proper. The RESET signal is transitioning from low to high as expected, which we have confirmed using a logic analyzer.

However, on the logic analyzer, the SPI clock is showing 16-bit and 8-bit clock cycles instead of the expected 24-bit cycles.

Could you please guide us on how to resolve this issue? Is there anything that needs to be modified in the software or in the hardware design?

CLK, MISO, MOSI, CS in 25.1



Thanks and Regards,
Subashini

Hi SJagini 

After changing all the GPIOs to input/output in the FPGA design, we are now getting a 24-bit clock cycle, as shown in the attached Logic Analyzer image. However, after this data transmission, we are not getting a proper clock waveform. Additionally, both the MISO and MOSI lines are going low.

With these changes, we are still encountering the same issue: Unsupported Product ID 0x0. Do we missing anything or need to be change, could you please share any inputs on this ?

Thanks and Regards,
Subashini

HI Subashini 

Hi SJagini 

Thank you for your response.

As per your suggestions, we regenerated the design and also compiled the ZCU102 design from the HDL provided by Analog Devices. We then converted it to our Versal device. However, after one 24-bit SPI clock cycle, the clock, MOSI, and MISO lines are going low.

In the Logic Analyzer, we are observing 0x5 on the MISO line, but when we add debug prints inside the  ad9361_spi_check function, we are getting 0x0 only.




Thanks and Regards,
Subashini

Hi SJagini 

The AD9361 chip initialization issue was resolved by referring to AMD's workaround.

https://adaptivesupport.amd.com/s/article/000037096?language=en_US

Thanks and Regards,
Subashini