Regarding IQ samples transfer from PL for AD9361

Hi Matry, do you have a functional testbench of your HDL?

the fmcomms2 project uses the AXI_AD9361 and a tb is available at https://github.com/analogdevicesinc/testbenches/blob/main/testbenches/project/fmcomms2

testbenches user guide at https://analogdevicesinc.github.io/testbenches/user_guide/build_tb.html

Looking at the fmcomms2 project, we have

axi_ad9461_dac_dma.m_axis -> util_ad9361_dac_upack.s_axis->fifo_rd_data[0-3]->axi_ad9361_dac_fifo->axi_ad9361

you need to provide, from the PL, an axis stream to util_ad9361_dac_upack.s_axis , that provides a axis_valid signal, and accepts back pressure from s_axis_ready.

After you manage a working testing bench, ensure on the software side you are properly activating the IPs, with all necessary drivers probed.

About dac_data_sel_s, it commes from the up_dac_channel, a shared ip inside the axi_ad9361 ip.

From the regmap > Dac channel > CHAN_CNTRLn_7 you select the data source, including an internal tone and testing ramp.

The register is at the source code at library/common/up_dac_channel.v#L390 (4'h6 -> 0x106 + 0x10*n at the doc, where n is the channel) (Here, for a no PS config, you could try hardcoding your data input as the default)
Regards,

Jorge

Hello Jorge, 

Thank you for the guidance. I am able to send the IQ data direct from PL.