Post Go back to editing

The ZCU102 supports a 61.44 MSPS sampling rate in the FMCOMMS5 design.

Category: Datasheet/Specs
Product Number: AD9361

Hello Team,

I referred to the FMCOMMS5 validation documentation, specifically the FMCOMMS5 Phase Synchronization page on the Analog Devices Wiki ( FMComms5 Phase Synchronization [Analog Devices Wiki] ). The reference mentions validation using a 30.72 MSPS sampling rate. Could you please confirm whether the ZCU102 supports operation with the FMCOMMS5 at a 61.44 MSPS sampling rate and an RX LO frequency of 2400 MHz? If supported, kindly let us know if there are any specific configuration requirements or recommended settings to achieve stable operation at this sampling rate.

Parents
  • Hi Team,

    Could you please validate the ZCU102 board with FMCOMMS5 on your side and confirm the sampling rate range over which MCS (Multi-Chip Sync) works reliably?

    Specifically, we would like to know:

    1. Up to what sampling rate is synchronization stable on both AD9361 chips?
    2. What behavior is observed beyond that range?
    3. Are there any required updates in the HDL design, DMA configuration, clocking, or device tree to support stable operation at 61.44 MSPS?
    4. Are there any known FPGA limitations (DDR bandwidth, HP port throughput, AXI/DMA burst settings, etc.) affecting performance at 61.44 MSPS?

    We are observing stable synchronization only up to a certain sampling rate, and beyond that, waveform instability/noise appears. Your validation results and recommended configuration would help us proceed further.

    Looking forward to your guidance.

    Regards,
    Sasikumar

Reply
  • Hi Team,

    Could you please validate the ZCU102 board with FMCOMMS5 on your side and confirm the sampling rate range over which MCS (Multi-Chip Sync) works reliably?

    Specifically, we would like to know:

    1. Up to what sampling rate is synchronization stable on both AD9361 chips?
    2. What behavior is observed beyond that range?
    3. Are there any required updates in the HDL design, DMA configuration, clocking, or device tree to support stable operation at 61.44 MSPS?
    4. Are there any known FPGA limitations (DDR bandwidth, HP port throughput, AXI/DMA burst settings, etc.) affecting performance at 61.44 MSPS?

    We are observing stable synchronization only up to a certain sampling rate, and beyond that, waveform instability/noise appears. Your validation results and recommended configuration would help us proceed further.

    Looking forward to your guidance.

    Regards,
    Sasikumar

Children
No Data