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AD9361 Recommended for New Designs
The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and 4G base station applications....
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AD9361 on Analog.com

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The ZCU102 supports a 61.44 MSPS sampling rate in the FMCOMMS5 design.

		
	
				

			

									
					    sasikumar
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 13, 2026 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Datasheet/Specs
    
    		        		            		    
    Product Number:  AD9361  
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hello Team,
    

    I referred to the FMCOMMS5 validation documentation, specifically the FMCOMMS5 Phase Synchronization page on the Analog Devices Wiki ( FMComms5 Phase Synchronization [Analog Devices Wiki] ). The reference mentions validation using a 30.72 MSPS sampling rate. Could you please confirm whether the ZCU102 supports operation with the FMCOMMS5 at a 61.44 MSPS sampling rate and an RX LO frequency of 2400 MHz? If supported, kindly let us know if there are any specific configuration requirements or recommended settings to achieve stable operation at this sampling rate.
    
			
    
			
									
		                             
                        

    
    
                                            
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 16, 2026 12:08 AM
            
            
						
			            		
      
		
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      HI  
      

      

      Yes — the ZCU102 does support FMCOMMS5 operation at 61.44 MSPS with an RX LO of 2400 MHz.
      

      

      

      

      ADI’s HDL reference designs for FMCOMMS5 were validated at:
      

        

      • 30.72 MSPS (documented in reference)
        • 

      • 61.44 MSPS (supported but less commonly tested or yet to be verified). Because limitation might come from FPGA and its DDR speed. Pls check on this configuration.
        • 

      

      

      If using IIO / libiio: Pls try with following commands to configure the device for 61.44MSPS
      

      ===========
      

      iio_attr -a -c ad9361-phy sampling_frequency 61440000
      

      iio_attr -a -c ad9361-phy rf_bandwidth 56000000 (recommended with 61.44 MSPS)
      

      ===========
      

      

      

      

      At 61.44 MSPS, all MCS (Multi-Chip Sync) functions work reliably as long as you following:
      

        

      • You use the ADI-provided HDL + Linux + device tree.
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      • You run the MCS sequence after setting the sample rate.
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      • You do not modify the clock routing to the two AD9361s.
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      Regards,
      

      SJ
      

      

      

      

      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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                on Feb 18, 2026 1:04 AM
            
            
						
			            		
        
		
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        Hi SJ,
        

        Could you please confirm whether the ZCU102 will reliably support operation at 61.44 MSPS with an LO frequency of 2400 MHz? Additionally, please let us know if there are any known limitations or specific configuration recommendations for stable performance at this sampling rate.
        

        Regards,
         Sasikumar
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Feb 19, 2026 9:24 AM
            
            
						
			            		
        
		
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        HI  

        As we haven't validated. I would recommend checking as i have mentioned in my earlier message. I have provided the key things to check.
        

        

        Regards,
        

        Sai
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Feb 20, 2026 3:27 AM
            
            
						
			            		
          
		
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          Hi Sai,
          Could you please clarify what exact FPGA limitation (DDR speed, HP port bandwidth, AXI/DMA burst, etc...) might cause this issue at 61.44 MSPS on ZCU102?
          

          Regards,
          Sasikumar
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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                on Mar 2, 2026 7:27 AM
            
            
						
			            		
            
		
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            Hi Team,
            

            Could you please validate the ZCU102 board with FMCOMMS5 on your side and confirm the sampling rate range over which MCS (Multi-Chip Sync) works reliably?
            

            Specifically, we would like to know:
            

              

            1. Up to what sampling rate is synchronization stable on both AD9361 chips?
              2. 

            2. What behavior is observed beyond that range?
              3. 

            3. Are there any required updates in the HDL design, DMA configuration, clocking, or device tree to support stable operation at 61.44 MSPS?
              4. 

            4. Are there any known FPGA limitations (DDR bandwidth, HP port throughput, AXI/DMA burst settings, etc.) affecting performance at 61.44 MSPS?
              5. 

            

            We are observing stable synchronization only up to a certain sampling rate, and beyond that, waveform instability/noise appears. Your validation results and recommended configuration would help us proceed further.
            

            Looking forward to your guidance.
            

            Regards,
             Sasikumar
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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