Category: Software
Product Number: AD9364
Hi Team ,
I'm attempting to build the HDL Reference Design for the Zedboard with AD9364 on Linux using the latest branch. To bypass version checking, I exported ADI_IGNORE_VERSION_CHECK=1 before running make. However, the build is still failing for some unknown IP Blocks as below ,
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell sys_concat_intc
ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name sys_concat_intc .
I've verified that ADI_IGNORE_VERSION_CHECK is properly set (echo confirms it returns 1), so the export command is working correctly. Interestingly, when I checkout the 2021_r2 branch( as I'm using VIVADO 2021.2 ), clone it, and run make, the build completes successfully.
What could be causing this IP Blocks issue specifically with the latest branch?I Have attached the screenshot and log file here for your Reference .
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source system_project.tcl
# source ../../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../"]]
## if [info exists ::env(ADI_HDL_DIR)] {
## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## } else {
## set env(ADI_HDL_DIR) $ad_hdl_dir
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
## set required_vivado_version "2025.1"
## if {[info exists ::env(REQUIRED_VIVADO_VERSION)]} {
## set required_vivado_version $::env(REQUIRED_VIVADO_VERSION)
## } elseif {[info exists REQUIRED_VIVADO_VERSION]} {
## set required_vivado_version $REQUIRED_VIVADO_VERSION
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
## set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
## set IGNORE_VERSION_CHECK 0
## }
## if {![info exists REQUIRED_QUARTUS_VERSION]} {
## set REQUIRED_QUARTUS_VERSION "25.1.0"
## }
## set required_lattice_version "2024.2"
## if {[info exists ::env(REQUIRED_LATTICE_VERSION)]} {
## set required_lattice_version $::env(REQUIRED_LATTICE_VERSION)
## } elseif {[info exists REQUIRED_LATTICE_VERSION]} {
## set required_lattice_version $REQUIRED_LATTICE_VERSION
## }
## proc get_env_param {name default_value} {
## if [info exists ::env($name)] {
## puts "Getting from environment the parameter: $name=$::env($name) "
## return $::env($name)
## } else {
## return $default_value
## }
## }
# source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
## if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
## if {[string equal $::env(ADI_USE_OOC_SYNTHESIS) n]} {
## set ADI_USE_OOC_SYNTHESIS 0
## } else {
## set ADI_USE_OOC_SYNTHESIS 1
## }
## } elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
## set ADI_USE_OOC_SYNTHESIS 1
## }
## if {![info exists ::env(ADI_MAX_OOC_JOBS)]} {
## set ADI_MAX_OOC_JOBS 4
## } else {
## set ADI_MAX_OOC_JOBS $::env(ADI_MAX_OOC_JOBS)
## }
## set ADI_USE_INCR_COMP 1
## set ADI_POWER_OPTIMIZATION 0
## if {![info exists ::env(ADI_GENERATE_BIN)]} {
## set ADI_GENERATE_BIN 0
## } else {
## if {[string equal $::env(ADI_GENERATE_BIN) n]} {
## set ADI_GENERATE_BIN 0
## } else {
## set ADI_GENERATE_BIN 1
## }
## }
## set p_board "not-applicable"
## set p_device "none"
## set sys_zynq 1
## set p_prcfg_init ""
## set p_prcfg_list ""
## set p_prcfg_status ""
## proc adi_project {project_name {mode 0} {parameter_list {}} } {
##
## set device ""
## set board ""
##
## # Determine the device based on the board name
## if [regexp "_ac701" $project_name] {
## set device "xc7a200tfbg676-2"
## set board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
## }
## if [regexp "_vcu118" $project_name] {
## set device "xcvu9p-flga2104-2L-e"
## set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
## }
## if [regexp "_kcu105" $project_name] {
## set device "xcku040-ffva1156-2-e"
## set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
## }
## if [regexp "_zed" $project_name] {
## set device "xc7z020clg484-1"
## set board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
## }
## if [regexp "_coraz7s" $project_name] {
## set device "xc7z007sclg400-1"
## set board "not-applicable"
## }
## if [regexp "_microzed" $project_name] {
## set device "xc7z010clg400-1"
## set board "not-applicable"
## }
## if [regexp "_zc702" $project_name] {
## set device "xc7z020clg484-1"
## set board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
## }
## if [regexp "_zc706" $project_name] {
## set device "xc7z045ffg900-2"
## set board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
## }
## if [regexp "_mitx045" $project_name] {
## set device "xc7z045ffg900-2"
## set board "not-applicable"
## }
## if [regexp "_zcu102" $project_name] {
## set device "xczu9eg-ffvb1156-2-e"
## set board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
## }
## if [regexp "_vmk180_es1" $project_name] {
## enable_beta_device xcvm*
## xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
## xhub::install [xhub::get_xitems xilinx.com:xilinx_board_store:vmk180_es:*] -quiet
## set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
## set device "xcvm1802-vsva2197-2MP-e-S-es1"
## set board [lindex [lsearch -all -inline [get_board_parts] *vmk180_es*] end]
## }
## if [regexp "_vmk180" $project_name] {
## set device "xcvm1802-vsva2197-2MP-e-S"
## set board [lindex [lsearch -all -inline [get_board_parts] *vmk180*] end]
## }
## if [regexp "_vck190" $project_name] {
## set device "xcvc1902-vsva2197-2MP-e-S"
## set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end]
## }
## if [regexp "_vpk180" $project_name] {
## set device "xcvp1802-lsvc4072-2MP-e-S"
## set board [lindex [lsearch -all -inline [get_board_parts] *vpk180*] end]
## }
## if [regexp "_vc709" $project_name] {
## set device "xc7vx690tffg1761-2"
## set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end]
## }
## if [regexp "_kv260" $project_name] {
## set device "xck26-sfvc784-2LV-c"
## set board [lindex [lsearch -all -inline [get_board_parts] *kv260*] end]
## }
## if [regexp "_k26" $project_name] {
## set device "xck26-sfvc784-2LVI-i"
## set board [lindex [lsearch -all -inline [get_board_parts] *k26*] end]
## }
##
## adi_project_create $project_name $mode $parameter_list $device $board
## }
## proc adi_project_create {project_name mode parameter_list device {board "not-applicable"}} {
##
## global ad_hdl_dir
## global ad_ghdl_dir
## global ad_project_dir
## global p_board
## global p_device
## global sys_zynq
## global required_vivado_version
## global IGNORE_VERSION_CHECK
## global ADI_USE_OOC_SYNTHESIS
## global ADI_USE_INCR_COMP
## global use_smartconnect
##
## if {![info exists ::env(ADI_PROJECT_DIR)]} {
## set actual_project_name $project_name
## } else {
## set actual_project_name "$::env(ADI_PROJECT_DIR)${project_name}"
## }
##
## ## update the value of $p_device only if it was not already updated elsewhere
## if {$p_device eq "none"} {
## set p_device $device
## }
## set p_board $board
##
## set use_smartconnect 1
## if [regexp "^xc7z" $p_device] {
## # SmartConnect has higher resource utilization and worse timing closure on older families
## set use_smartconnect 0
## }
##
## if [regexp "^xc7z" $p_device] {
## set sys_zynq 1
## } elseif [regexp "^xck26" $p_device] {
## set sys_zynq 2
## } elseif [regexp "^xczu" $p_device] {
## set sys_zynq 2
## } elseif [regexp "^xcv\[ecmph\]" $p_device] {
## set sys_zynq 3
## } else {
## set sys_zynq 0
## }
##
## set VIVADO_VERSION [version -short]
## if {$IGNORE_VERSION_CHECK} {
## if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} {
## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
## puts -nonewline "expected $required_vivado_version, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## }
## } else {
## if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} {
## puts -nonewline "ERROR: vivado version mismatch; "
## puts -nonewline "expected $required_vivado_version, "
## puts -nonewline "got $VIVADO_VERSION.\n"
## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
## exit 2
## }
## }
##
## if {[info exists ::env(ADI_MATLAB)]} {
## set ADI_MATLAB 1
## set actual_project_name "$ad_hdl_dir/vivado_prj"
## if {$mode != 0} {
## puts -nonewline "MATLAB builds do not support mode 2"
## exit 2
## }
## } else {
## set ADI_MATLAB 0
## }
##
## if {$mode == 0} {
## set project_system_dir "${actual_project_name}.srcs/sources_1/bd/system"
## if {$ADI_MATLAB == 0} {
## create_project ${actual_project_name} . -part $p_device -force
## }
## } else {
## set project_system_dir "${actual_project_name}.srcs/sources_1/bd/system"
## create_project -in_memory -part $p_device
## }
##
## if {$mode == 1} {
## file mkdir ${actual_project_name}.data
## }
##
## if {$p_board ne "not-applicable"} {
## set_property board_part $p_board [current_project]
## }
##
## if {$ADI_MATLAB == 0} {
## set lib_dirs $ad_hdl_dir/library
## } else {
## set lib_dirs [get_property ip_repo_paths [current_fileset]]
## lappend lib_dirs $ad_hdl_dir/library
## }
## if {[info exists ::env(ADI_GHDL_DIR)]} {
## if {$ad_hdl_dir ne $ad_ghdl_dir} {
## lappend lib_dirs $ad_ghdl_dir/library
## }
## }
##
## # Set a common IP cache for all projects
## if {$ADI_USE_OOC_SYNTHESIS == 1} {
## if {[file exists $ad_hdl_dir/ipcache] == 0} {
## file mkdir $ad_hdl_dir/ipcache
## }
## config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
## }
##
## set_property ip_repo_paths $lib_dirs [current_fileset]
## update_ip_catalog
##
## ## Load custom message severity definitions
##
## if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} {
## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
## }
##
## ## In Vivado there is a limit for the number of warnings and errors which are
## ## displayed by the tool for a particular error or warning; the default value
## ## of this limit is 100.
## ## Overrides the default limit to 2000.
## set_param messaging.defaultLimit 2000
##
## # Set parameters of the top level file
## # Make the same parameters available to system_bd.tcl
## set proj_params [get_property generic [current_fileset]]
## foreach {param value} $parameter_list {
## lappend proj_params $param=$value
## set ad_project_params($param) $value
## }
## set_property generic $proj_params [current_fileset]
##
## create_bd_design "system"
## source system_bd.tcl
##
## save_bd_design
## validate_bd_design
##
## if {$ADI_USE_OOC_SYNTHESIS == 1} {
## set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd]
## } else {
## set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd]
## }
## generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
## if {$ADI_USE_OOC_SYNTHESIS == 1} {
## export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet
## create_ip_run [get_files $project_system_dir/system.bd]
## }
## make_wrapper -files [get_files $project_system_dir/system.bd] -top
##
## if {$mode == 0} {
## import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
## } else {
## write_hwdef -file "${actual_project_name}.data/$project_name.hwdef"
## }
##
## if {$ADI_USE_INCR_COMP == 1} {
## if {[file exists ./reference.dcp]} {
## set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
## }
## }
##
## }
## proc adi_project_files {project_name project_files} {
## global ADI_POST_ROUTE_POD_PRE_SCRIPT
## global ADI_POST_ROUTE_SCRIPT
##
## foreach pfile $project_files {
## if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
## add_files -norecurse -fileset constrs_1 $pfile
## } else {
## add_files -norecurse -fileset sources_1 $pfile
## }
## }
##
## if {[info exists ADI_POST_ROUTE_POD_PRE_SCRIPT]} {
## add_files -fileset utils_1 -norecurse ${ADI_POST_ROUTE_POD_PRE_SCRIPT}
## }
## if {[info exists ADI_POST_ROUTE_SCRIPT]} {
## add_files -fileset utils_1 -norecurse ${ADI_POST_ROUTE_SCRIPT}
## }
##
## # NOTE: top file name is always system_top
## set_property top system_top [current_fileset]
## }
## proc adi_xcvr_project {parameters_for_make} {
##
## global ad_hdl_dir
##
## set project_name "xcvr_wizard"
## set current_dir [pwd]
## set carrier_name [file tail $current_dir]
##
## switch $carrier_name {
## "zc706" {
## set xcvr_type GTXE2
## }
## "kc705" {
## set xcvr_type GTXE2
## }
## "zed" {
## set xcvr_type GTXE2
## }
## "vc707" {
## set xcvr_type GTXE2
## }
## "kcu105" {
## set xcvr_type GTHE3
## }
## "zcu102" {
## set xcvr_type GTHE4
## }
## "vcu118" {
## set xcvr_type GTYE4
## }
## "vcu128" {
## set xcvr_type GTYE4
## }
## default {
## puts "ERROR adi_project_make: Unsupported carrier (device)."
## return 1
## }
## }
##
## set make_command "make"
## set adi_project_dir_path [file join $ad_hdl_dir/projects $project_name $carrier_name]
## cd $adi_project_dir_path
##
## set adi_dir_env ""
## if {[info exists ::env(ADI_PROJECT_DIR)] && $::env(ADI_PROJECT_DIR) ne ""} {
## set adi_dir_env [file tail [string trimright $::env(ADI_PROJECT_DIR) "/"]]
## }
##
## if {[llength $parameters_for_make] > 0} {
##
## set formatted_params {}
## set gt_xcvr_file {}
##
## foreach {key value} $parameters_for_make {
## lappend formatted_params "$key=$value"
## set key_parsed [string map {"LANE_" "" "_" ""} $key]
## set value_parrsed [string map {. _} $value]
## set ad_project_make_params($key) $value_parrsed
## set tok "${key_parsed}${value_parrsed}"
##
## if {$adi_dir_env eq "" || ![regexp "(^|_)${tok}(_|$)" $adi_dir_env]} {
## set gt_xcvr_file [linsert $gt_xcvr_file 0 "$tok"]
## }
## }
##
## append make_command " " [join $formatted_params " "]
## set gt_xcvr_file [join $gt_xcvr_file "_"]
## set config_parser_dir_name "${xcvr_type}_${ad_project_make_params(PLL_TYPE)}_${ad_project_make_params(LANE_RATE)}_${ad_project_make_params(REF_CLK)}"
## set file_local_param [string tolower $config_parser_dir_name]
## append file_local_param "_common.v"
## }
##
## eval exec $make_command
## cd $current_dir
##
## if {$adi_dir_env ne ""} {
## if {$gt_xcvr_file eq ""} {
## append adi_project_dir_path "/${::env(ADI_PROJECT_DIR)}${project_name}_${carrier_name}.gen/sources_1/ip/${xcvr_type}_cfng.txt"
## } else {
## append adi_project_dir_path "/$gt_xcvr_file\_$::env(ADI_PROJECT_DIR)${project_name}_${carrier_name}.gen/sources_1/ip/${xcvr_type}_cfng.txt"
## }
## } else {
## append adi_project_dir_path "/$gt_xcvr_file/${project_name}_${carrier_name}.gen/sources_1/ip/${xcvr_type}_cfng.txt"
## }
##
## set config_dir_path [file dirname $adi_project_dir_path]
## set file_local_param_path ""
##
## if {$xcvr_type == "GTXE2"} {
## set file_local_param_path [file join $config_dir_path $config_parser_dir_name $file_local_param]
## }
##
## return [dict create "cfng_file_path" $adi_project_dir_path "param_file_path" $file_local_param_path]
## }
## proc adi_project_run {project_name} {
##
## global ad_project_dir
## global sys_zynq
## global ADI_POWER_OPTIMIZATION
## global ADI_USE_OOC_SYNTHESIS
## global ADI_MAX_OOC_JOBS
## global ADI_GENERATE_BIN
## global ADI_POST_ROUTE_POD_PRE_SCRIPT
## global ADI_POST_ROUTE_SCRIPT
##
## if {[info exists ::env(ADI_MAX_THREADS)]} {
## set_param general.maxThreads ${::env(ADI_MAX_THREADS)}
## puts "INFO: maxThreads set to ${::env(ADI_MAX_THREADS)}"
## }
##
## if {![info exists ::env(ADI_PROJECT_DIR)]} {
## set actual_project_name $project_name
## set ad_project_dir ""
## } else {
## set actual_project_name "$::env(ADI_PROJECT_DIR)${project_name}"
## set ad_project_dir "$::env(ADI_PROJECT_DIR)"
## }
## if {[info exists ::env(ADI_SKIP_SYNTHESIS)]} {
## puts "Skipping synthesis"
## return
## }
##
## if {$ADI_USE_OOC_SYNTHESIS == 1} {
## launch_runs -jobs $ADI_MAX_OOC_JOBS system_*_synth_1 synth_1
## } else {
## launch_runs synth_1
## }
## wait_on_run synth_1
## open_run synth_1
## report_timing_summary -file ${ad_project_dir}timing_synth.log
##
## if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
## set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
## }
##
## if {$ADI_POWER_OPTIMIZATION == 1} {
## set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
## set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
## }
##
## set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
##
## if {[info exists ADI_POST_ROUTE_POD_PRE_SCRIPT]} {
## set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
## set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.TCL.PRE [ get_files ${ADI_POST_ROUTE_POD_PRE_SCRIPT} -of [get_fileset utils_1] ] [get_runs impl_1]
## }
## if {[info exists ADI_POST_ROUTE_SCRIPT]} {
## set_property STEPS.ROUTE_DESIGN.TCL.POST [ get_files ${ADI_POST_ROUTE_SCRIPT} -of [get_fileset utils_1] ] [get_runs impl_1]
## }
##
## launch_runs impl_1 -to_step write_bitstream
## wait_on_run impl_1
## open_run impl_1
## report_timing_summary -warn_on_violation -file ${ad_project_dir}timing_impl.log
##
## if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
## set csv_file ${ad_project_dir}resource_utilization.csv
## if {[ catch {
## xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
## set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
## set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
## set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
## set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
##
## set fileRead [open $csv_file r]
## set lines [split [read $fileRead] "\n"]
## set names_line [lindex $lines end-3]
## set values_line [lindex $lines end-2]
## close $fileRead
##
## set fileWrite [open $csv_file w]
## puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
## puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
## close $fileWrite
## } issue ] != 0 } {
## puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
## }
##
## # Define a list of IPs for which to generate report utilization
## set IP_list {
## ad_ip_jesd_204_tpl_adc
## ad_ip_jesd_204_tpl_dac
## axi_jesd204_rx
## axi_jesd204_tx
## jesd204_rx
## jesd204_tx
## axi_adxcvr
## util_adxcvr
## axi_dmac
## util_cpack2
## util_upack2
## }
##
## foreach IP_name $IP_list {
## set output_file ${ad_project_dir}${IP_name}_resource_utilization.log
## file delete $output_file
## foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
## report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
## report_property $IP_instance -file $output_file -append -quiet
## set report_file [ open $output_file a ]
## puts $report_file "\n\n\n"
## close $report_file
## }
## }
## } else {
## puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
## }
##
## ## Extract IP ports and their properties
##
## if {[info exists ::env(ADI_EXTRACT_PORTS)]} {
##
## set p_output_file ports_properties.txt
##
## # Define a list of IPs for which to generate the ports properties and nets report
## set P_IP_list {
## util_wfifo
## util_rfifo
## util_cpack2
## util_upack2
## ad_ip_jesd204_tpl_adc
## ad_ip_jesd204_tpl_dac
## rx_fir_decimator
## tx_fir_interpolator
## axi_ad9361
## axi_adrv9009
## }
##
## set fileWrite [open $p_output_file w]
##
## foreach P_IP_name $P_IP_list {
## foreach P_IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $P_IP_name || REF_NAME =~ $P_IP_name " ] {
## set P_IP_instance_name [regsub -all {i_system_wrapper\/system_i\/} $P_IP_instance {}]
## if { [regexp {adc_tpl_core} $P_IP_instance_name] } {
## set P_IP_INST [regsub -all {\/adc_tpl_core/inst} $P_IP_instance_name {}]
## puts "$P_IP_INST\n"
## } elseif { [regexp {dac_tpl_core} $P_IP_instance_name] } {
## set P_IP_INST [regsub -all {\/dac_tpl_core/inst} $P_IP_instance_name {}]
## puts "$P_IP_INST\n"
## } else {
## set P_IP_INST [regsub -all {\/inst} $P_IP_instance_name {}]
## puts "$P_IP_INST\n"
## }
## puts $fileWrite "\n$P_IP_INST properties: \n"
## set list_of_IP_ports [ get_bd_pins -of_objects [get_bd_cells $P_IP_INST]]
## foreach IP_port $list_of_IP_ports {
## set pin_direction [get_property DIR [get_bd_pins $IP_port]]
## set pin_path [get_property PATH [get_bd_pins $IP_port]]
## set pin_path_name [regsub {\/} $pin_path {}]
## set left [get_property LEFT [get_bd_pins $IP_port]]
## set right [get_property RIGHT [get_bd_pins $IP_port]]
## puts $fileWrite "direction $pin_direction \nMSB $left \nLSB $right \nname $pin_path_name"
## set net_info [get_bd_nets -of_objects [get_bd_pins $IP_port]]
## set net_name [regsub -all {\/} $net_info {}]
## puts $fileWrite "net $net_name\n"
## }
## }
## }
## close $fileWrite
##
## } else {
## puts "GENERATE_PORTS_REPORTS: IP ports properties and nets report files won't be generated because ADI_EXTRACT_PORTS env var is not set"
## }
##
## if {[info exists ::env(ADI_GENERATE_XPA)]} {
## set csv_file ${ad_project_dir}power_analysis.csv
## set Layers "8to11"
## set CapLoad "20"
## set ToggleRate "15.00000"
## set StatProb "0.500000"
##
## set_load $CapLoad [all_outputs]
## set_operating_conditions -board_layers $Layers
## set_switching_activity -default_toggle_rate $ToggleRate
## set_switching_activity -default_static_probability $StatProb
## set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
## set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
## report_power -file $csv_file
##
## set fileRead [open $csv_file r]
## set filecontent [read $fileRead]
## set input_list [split $filecontent "\n"]
##
## set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
## set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
## set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
## set junction_temp "[lindex [lindex $TextList 0] 5] *C"
## close $fileRead
##
## set fileWrite [open $csv_file w]
## puts $fileWrite "On-chip_power,Junction_temp"
## puts $fileWrite "$on_chip_pwr,$junction_temp"
## close $fileWrite
## } else {
## puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
## }
##
## # Look for undefined clocks which do not show up in the timing summary
## set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
## if {[regexp { (\d+) register} $timing_check -> num_regs]} {
##
## if {[info exist num_regs]} {
## if {$num_regs > 0} {
## puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
## check_timing -override_defaults no_clock -verbose -file ${ad_project_dir}no_clock.log
## }
## }
##
## } else {
## puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
## }
##
## file mkdir ${actual_project_name}.sdk
##
## set timing_string $[report_timing_summary -return_string]
## if { [string match "*VIOLATED*" $timing_string] == 1 ||
## [string match "*Timing constraints are not met*" $timing_string] == 1} {
## write_hw_platform -fixed -force -include_bit -file ${actual_project_name}.sdk/system_top_bad_timing.xsa
## # Generate .bin file only for non Versal designs
## if {$ADI_GENERATE_BIN == 1} {
## if {$sys_zynq == 3} {
## puts "Bin generation skipped, Versal families do not support it."
## } else {
## write_bitstream -bin_file ${actual_project_name}.sdk/system_top_bad_timing.bit
## }
## }
## return -code error [format "ERROR: Timing Constraints NOT met!"]
## } else {
## write_hw_platform -fixed -force -include_bit -file ${actual_project_name}.sdk/system_top.xsa
## # Generate .bin file only for non Versal designs
## if {$ADI_GENERATE_BIN == 1} {
## if {$sys_zynq == 3} {
## puts "Bin generation skipped, Versal families do not support it."
## } else {
## write_bitstream -bin_file ${actual_project_name}.sdk/system_top.bit
## }
## }
## }
## }
## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
##
## global p_device
## global ad_project_dir
##
## if {![info exists ::env(ADI_PROJECT_DIR)]} {
## set actual_project_name $project_name
## } else {
## set actual_project_name "$::env(ADI_PROJECT_DIR)${project_name}"
## }
##
## set p_prefix "${actual_project_name}.data/$project_name"
##
## if {$prcfg_name eq ""} {
##
## read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
## read_verilog $hdl_files
## read_xdc $xdc_files
##
## synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
## write_checkpoint -force $p_prefix.synth.dcp
## close_project
##
## } else {
##
## create_project -in_memory -part $p_device
## read_verilog $hdl_files
## synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
## write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
## close_project
## }
## }
## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
##
## global p_device
## global p_prcfg_init
## global p_prcfg_list
## global p_prcfg_status
## global ad_project_dir
##
## if {![info exists ::env(ADI_PROJECT_DIR)]} {
## set actual_project_name $project_name
## } else {
## set actual_project_name "$::env(ADI_PROJECT_DIR)${project_name}"
## }
##
## set p_prefix "${actual_project_name}.data/$project_name"
##
## if {$prcfg_name eq "default"} {
## set p_prcfg_status 0
## set p_prcfg_list ""
## set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
## file mkdir $project_name.sdk
## }
##
## if {$prcfg_name eq "default"} {
##
## open_checkpoint $p_prefix.synth.dcp -part $p_device
## read_xdc $xdc_files
## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
## set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
## opt_design > $p_prefix.${prcfg_name}_opt.rds
## write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
## place_design > $p_prefix.${prcfg_name}_place.rds
## route_design > $p_prefix.${prcfg_name}_route.rds
##
## } else {
##
## open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
## lock_design -level routing
## read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
## read_xdc $xdc_files
## opt_design > $p_prefix.${prcfg_name}_opt.rds
## place_design > $p_prefix.${prcfg_name}_place.rds
## route_design > $p_prefix.${prcfg_name}_route.rds
## }
##
## write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
## report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
## report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
##
## if [expr [get_property SLACK [get_timing_paths]] < 0] {
## set p_prcfg_status 1
## puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
## }
##
## write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
## update_design -cell i_prcfg -black_box
## write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
## open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
## write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
## write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
##
## if {$prcfg_name ne "default"} {
## lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
## }
##
## if {$prcfg_name eq "default"} {
## file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
## }
## }
## proc adi_project_verify {project_name} {
##
## # checkpoint for the default design
## global p_prcfg_init
## # list of checkpoints with all the PRs integrated into the default design
## global p_prcfg_list
## global p_prcfg_status
##
## set p_prefix "${actual_project_name}.data/$project_name"
##
## pr_verify -full_check -initial $p_prcfg_init \
## -additional $p_prcfg_list \
## -file $p_prefix.prcfg_verify.log
##
## if {$p_prcfg_status == 1} {
## return -code error [format "ERROR: Timing Constraints NOT met!"]
## }
## }
# source $ad_hdl_dir/projects/scripts/adi_board.tcl
## set sys_hpc0_interconnect_index -1
## set sys_hpc1_interconnect_index -1
## set sys_hp0_interconnect_index -1
## set sys_hp1_interconnect_index -1
## set sys_hp2_interconnect_index -1
## set sys_hp3_interconnect_index -1
## set sys_mem_interconnect_index -1
## set sys_mem_clk_index 0
## set xcvr_index -1
## set xcvr_tx_index 0
## set xcvr_rx_index 0
## set xcvr_instance NONE
## set use_smartconnect 1
## proc ad_ip_instance {i_ip i_name {i_params {}}} {
## set ip_type ip
## set ip_def [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
## design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""]
## if {[string match "*inline_hdl*" $ip_def]} {
## set ip_type inline_hdl
## }
## set cell [create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}]
## if {$i_params != {}} {
## set config {}
## # Add CONFIG. prefix to all config options
## foreach {k v} $i_params {
## lappend config "CONFIG.$k" $v
## }
## set_property -dict $config $cell
## }
## }
## proc ad_ip_parameter {i_name i_param i_value} {
##
## set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
## }
## proc ad_connect_type {p_name} {
##
## set m_name ""
##
## if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
##
## return $m_name
## }
## proc ad_connect_int_class {p_name} {
##
## set m_name ""
##
## if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
## # All ports can be handled as pins
## # if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
## # if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
## if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
##
## if {!($m_name eq "")} {
## return [get_property CLASS $m_name]
## }
##
## if {$p_name eq "GND" || $p_name eq "VCC"} {
## return "const"
## }
##
## return "newnet"
## }
## proc ad_connect_int_get_const {name width} {
## switch $name {
## GND {
## set value 0
## }
## VCC {
## set value [expr (1 << $width) - 1]
## }
## default {
## error "ERROR: ad_connect_int_get_const: Unhandled constant name $name"
## }
## }
##
## set cell_name "$name\_$width"
##
## set cell [get_bd_cells -quiet $cell_name]
## if {$cell eq ""} {
## # Create new constant source
## ad_ip_instance ilconstant $cell_name
## set cell [get_bd_cells -quiet $cell_name]
## set_property CONFIG.CONST_WIDTH $width $cell
## set_property CONFIG.CONST_VAL $value $cell
## }
##
## return $cell
## }
## proc ad_connect_int_width {obj} {
## if {$obj eq ""} {
## error "ERROR: ad_connect_int_width: No object provided."
## }
##
## set classname [get_property -quiet CLASS $obj]
## if {$classname eq ""} {
## error "ERROR: ad_connect_int_width: Cannot determine width of class-less object: $obj"
## }
## if {[string first intf $classname] != -1} {
## error "ERROR: ad_connect_int_width: Cannot determine width of interface object: $obj ($classname)"
## }
##
## if {([get_property -quiet LEFT $obj] eq "") || ([get_property -quiet RIGHT $obj] eq "")} {
## return 1
## }
##
## set left [get_property LEFT $obj]
## set right [get_property RIGHT $obj]
##
## set high [expr max($left,$right)]
## set low [expr min($left,$right)]
##
## return [expr {1 + $high - $low}]
## }
## proc ad_connect {name_a name_b} {
## set type_a [ad_connect_int_class $name_a]
## set type_b [ad_connect_int_class $name_b]
##
## set obj_a [ad_connect_type $name_a]
## set obj_b [ad_connect_type $name_b]
##
## if {!([string first intf $type_a]+1) != !([string first intf $type_b]+1)} {
## error "ERROR: ad_connect: Cannot connect non-interface to interface: $name_a ($type_a) <-/-> $name_b ($type_b)"
## }
##
## switch $type_a,$type_b {
## newnet,newnet {
## error "ERROR: ad_connect: Cannot create connection between two new nets: $name_a <-/-> $name_b"
## }
## const,const {
## error "ERROR: ad_connect: Cannot connect constant to constant: $name_a <-/-> $name_b"
## }
## bd_net,bd_net -
## bd_intf_net,bd_intf_net {
## error "ERROR: ad_connect: Cannot connect (intf) net to (intf) net: $name_a ($type_a) <-/-> $name_b ($type_b)"
## }
## bd_net,newnet -
## newnet,bd_net {
## error "ERROR: ad_connect: Cannot connect existing net to new net: $name_a ($type_a) <-/-> $name_b ($type_b)"
## }
## const,newnet -
## newnet,const {
## error "ERROR: ad_connect: Cannot connect new network to constant, instead you should connect to the constant directly: $name_a ($type_a) <-/-> $name_b ($type_b)"
## }
##
## bd_pin,bd_pin {
## connect_bd_net $obj_a $obj_b
## puts "connect_bd_net $obj_a $obj_b"
## return
## }
## bd_net,bd_pin {
## connect_bd_net -net $obj_a $obj_b
## puts "connect_bd_net -net $obj_a $obj_b"
## return
## }
## bd_pin,bd_net {
## connect_bd_net -net $obj_b $obj_a
## puts "connect_bd_net -net $obj_b $obj_a"
## return
## }
## bd_pin,newnet {
## connect_bd_net -net $name_b $obj_a
## puts "connect_bd_net -net $name_b $obj_a"
## return
## }
## newnet,bd_pin {
## connect_bd_net -net $name_a $obj_b
## puts "connect_bd_net -net $name_a $obj_b"
## return
## }
## bd_intf_pin,bd_intf_pin {
## connect_bd_intf_net $obj_a $obj_b
## puts "connect_bd_intf_net $obj_a $obj_b"
## return
## }
## const,bd_pin -
## const,bd_net {
## # Handled after the switch statement
## }
## bd_net,const -
## bd_pin,const {
## # Swap vars
## set tmp $obj_a
## set obj_a $obj_b
## set obj_b $tmp
## set tmp $name_a
## set name_a $name_b
## set name_b $tmp
## # Handled after the switch statement
## }
## default {
## error "ERROR: ad_connect: Cannot connect, case unhandled: $name_a ($type_a) <-/-> $name_b ($type_b)"
## }
## }
##
## # Continue working on nets that connect to constant. obj_b is the net/pin
## set width [ad_connect_int_width $obj_b]
## set cell [ad_connect_int_get_const $name_a $width]
## connect_bd_net [get_bd_pin $cell/dout] $obj_b
## puts "connect_bd_net [get_bd_pin $cell/dout] $obj_b"
## }
## proc ad_disconnect {p_name_1 p_name_2} {
##
## set m_name_1 [ad_connect_type $p_name_1]
## set m_name_2 [ad_connect_type $p_name_2]
##
## if {[get_property CLASS $m_name_1] eq "bd_net"} {
## disconnect_bd_net $m_name_1 $m_name_2
## return
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_port"} {
## delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
## [find_bd_objs -relation connected_to $m_name_1]]
## delete_bd_objs -quiet $m_name_1
## return
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_pin"} {
## delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
## [find_bd_objs -relation connected_to $m_name_1]]
## delete_bd_objs -quiet $m_name_1
## return
## }
##
## if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
## delete_bd_objs -quiet [get_bd_intf_nets -of_objects [get_bd_intf_ports $m_name_1]]
## delete_bd_objs -quiet [get_bd_intf_ports $m_name_1]
## return
## }
## }
## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {link_clk {}} {device_clk {}} {num_of_max_lanes -1} {partial_lane_map {}} {connect_empty_lanes 1}} {
##
## global xcvr_index
## global xcvr_tx_index
## global xcvr_rx_index
## global xcvr_instance
##
## set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
## set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
##
## set xcvr_type [get_property CONFIG.XCVR_TYPE [get_bd_cells $u_xcvr]]
##
## set link_mode_u [get_property CONFIG.LINK_MODE [get_bd_cells $u_xcvr]]
## set link_mode_a [get_property CONFIG.LINK_MODE [get_bd_cells $a_xcvr]]
##
## if {$link_mode_u != $link_mode_a} {
## puts "CRITICAL WARNING: LINK_MODE parameter mismatch between $u_xcvr ($link_mode_u) and $a_xcvr ($link_mode_a)"
## }
## set link_mode $link_mode_u
##
## set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
##
## if {$jesd204_bd_type == "hier"} {
## set jesd204_type 0
## } else {
## set jesd204_type 1
## }
##
## if {$xcvr_instance ne $u_xcvr} {
## set xcvr_index [expr ($xcvr_index + 1)]
## set xcvr_tx_index 0
## set xcvr_rx_index 0
## set xcvr_instance $u_xcvr
## }
##
## set txrx "rx"
## set data_dir "I"
## set ctrl_dir "O"
## set index $xcvr_rx_index
##
## if {$tx_or_rx_n == 1} {
##
## set txrx "tx"
## set data_dir "O"
## set ctrl_dir "I"
## set index $xcvr_tx_index
## }
##
## set m_sysref ${txrx}_sysref_${index}
## set m_sync ${txrx}_sync_${index}
## set m_data ${txrx}_data
##
## if {$xcvr_index >= 1} {
##
## set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
## set m_sync ${txrx}_sync_${xcvr_index}_${index}
## set m_data ${txrx}_data_${xcvr_index}
## }
##
## if {$jesd204_type == 0} {
## set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
## } else {
## set num_of_links 1
## }
##
## set no_of_lanes [get_property CONFIG.NUM_LANES [get_bd_cells $a_jesd/$txrx]]
## set max_no_of_lanes $no_of_lanes
##
## if {$num_of_max_lanes != -1} {
## set max_no_of_lanes $num_of_max_lanes
## }
## create_bd_port -dir I $m_sysref
## create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
##
## set use_2x_clk 0
## if {$link_clk == {}} {
## # For 204C modes on GTH a 2x clock is required to drive the PCS
## # In such case set the xcvr out clock to be the double of the lane rate/66(40)
## # and use the secondary div2 clock output for the link clock
## if {$link_mode == 2 && ($xcvr_type == 5 || $xcvr_type == 8)} {
## set link_clk ${u_xcvr}/${txrx}_out_clk_div2_${index}
## set link_clk_2x ${u_xcvr}/${txrx}_out_clk_${index}
## set use_2x_clk 1
## } else {
## if {$partial_lane_map != {}} {
## set cur_index [lindex $partial_lane_map $index]
## set link_clk ${u_xcvr}/${txrx}_out_clk_${cur_index}
## } else {
## set link_clk ${u_xcvr}/${txrx}_out_clk_${index}
## }
## }
## set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
## set create_rst_gen 1
## } else {
## set rst_gen ${link_clk}_rstgen
## # Only create one reset gen per clock
## set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
## }
##
## if {$device_clk == {}} {
## set device_clk $link_clk
## } else {
## set rst_gen ${device_clk}_rstgen
## # Only create one reset gen per clock
## set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
## }
##
## if {${create_rst_gen}} {
## ad_ip_instance proc_sys_reset ${rst_gen}
## ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
## ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
## }
##
## if {$partial_lane_map != {}} {
## for {set n 0} {$n < $no_of_lanes} {incr n} {
##
## set phys_lane [lindex $partial_lane_map $n]
##
## if {$phys_lane != {}} {
## if {$jesd204_type == 0} {
## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
## } else {
## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
## }
## }
##
## if {$tx_or_rx_n == 0} {
## if {$jesd204_type == 0} {
## if {$link_mode == 1} {
## ad_connect ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
## }
## } else {
## ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
## }
## }
## }
## if {$connect_empty_lanes == 1} {
## for {set n 0} {$n < $max_no_of_lanes} {incr n} {
##
## set m [expr ($n + $index)]
##
## if {$lane_map != {}} {
## set phys_lane [lindex $lane_map $n]
## } else {
## set phys_lane $m
## }
##
## if {$tx_or_rx_n == 0} {
## ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
## }
##
## if {(($n%4) == 0) && ($qpll_enable == 1)} {
## ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
## }
## ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
## ad_connect ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
## if {$use_2x_clk == 1} {
## ad_connect ${link_clk_2x} ${u_xcvr}/${txrx}_clk_2x_${phys_lane}
## }
##
## create_bd_port -dir ${data_dir} ${m_data}_${m}_p
## create_bd_port -dir ${data_dir} ${m_data}_${m}_n
## ad_connect ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
## ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
## }
## } else {
## ## Do nothing, the connections will be done manually
## }
##
## } else {
## for {set n 0} {$n < $no_of_lanes} {incr n} {
##
## set m [expr ($n + $index)]
## if {$lane_map != {}} {
## set phys_lane [lindex $lane_map $n]
## } else {
## set phys_lane $m
## }
##
## if {$tx_or_rx_n == 0} {
## ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
## if {$jesd204_type == 0} {
## if {$link_mode == 1} {
## ad_connect ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
## }
## } else {
## ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
## }
## }
##
## if {(($n%4) == 0) && ($qpll_enable == 1)} {
## ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
## }
## ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
## ad_connect ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
## if {$use_2x_clk == 1} {
## ad_connect ${link_clk_2x} ${u_xcvr}/${txrx}_clk_2x_${phys_lane}
## }
## if {$phys_lane != {}} {
## if {$jesd204_type == 0} {
## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
## } else {
## ad_connect ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
## }
## }
##
## create_bd_port -dir ${data_dir} ${m_data}_${m}_p
## create_bd_port -dir ${data_dir} ${m_data}_${m}_n
## ad_connect ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
## ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
## }
##
## for {set n $no_of_lanes} {$n < $max_no_of_lanes} {incr n} {
##
## set m [expr ($n + $index)]
##
## if {$lane_map != {}} {
## set phys_lane [lindex $lane_map $n]
## } else {
## set phys_lane $m
## }
##
## create_bd_port -dir ${data_dir} ${m_data}_${m}_p
## create_bd_port -dir ${data_dir} ${m_data}_${m}_n
## ad_connect ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
## ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
## ad_connect ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
##
## if {$tx_or_rx_n == 0} {
## if {$jesd204_type == 0} {
## if {$link_mode == 1} {
## ad_connect ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
## }
## }
## }
## }
## }
##
## if {$jesd204_type == 0} {
## ad_connect ${a_jesd}/sysref $m_sysref
## if {$link_mode == 1} {
## ad_connect ${a_jesd}/sync $m_sync
## }
## ad_connect ${device_clk} ${a_jesd}/device_clk
## ad_connect ${link_clk} ${a_jesd}/link_clk
## } else {
## ad_connect ${a_jesd}/${txrx}_sysref $m_sysref
## ad_connect ${a_jesd}/${txrx}_sync $m_sync
## ad_connect ${device_clk} ${a_jesd}/${txrx}_core_clk
## ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
## ad_connect ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
## }
##
## if {$tx_or_rx_n == 0} {
## set xcvr_rx_index [expr ($xcvr_rx_index + $max_no_of_lanes)]
## }
##
## if {$tx_or_rx_n == 1} {
## set xcvr_tx_index [expr ($xcvr_tx_index + $max_no_of_lanes)]
## }
## }
## proc ad_xcvrpll {m_src m_dst} {
##
## foreach p_dst [get_bd_pins -quiet $m_dst] {
## connect_bd_net [ad_connect_type $m_src] $p_dst
## }
## }
## proc ad_mem_hpc0_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC0" $p_clk $p_name}
## }
## proc ad_mem_hpc1_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC1" $p_clk $p_name}
## }
## proc ad_mem_hp0_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
## if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
## if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
## }
## proc ad_mem_hp1_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
## if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
## if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
## }
## proc ad_mem_hp2_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
## if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
## if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
## }
## proc ad_mem_hp3_interconnect {p_clk p_name} {
##
## global sys_zynq
##
## if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
## if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
## if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
## if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
## if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
## if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
## }
## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
##
## global sys_zynq
## global sys_ddr_addr_seg
## global sys_hpc0_interconnect_index
## global sys_hpc1_interconnect_index
## global sys_hp0_interconnect_index
## global sys_hp1_interconnect_index
## global sys_hp2_interconnect_index
## global sys_hp3_interconnect_index
## global sys_mem_interconnect_index
## global sys_mem_clk_index
## global use_smartconnect
##
## set p_name_int $p_name
## set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
##
## set connect_type "smartconnect"
## if {$use_smartconnect == 0} {
## set connect_type "axi_interconnect"
## }
##
## if {$p_sel eq "SIM"} {
## if {$sys_mem_interconnect_index < 0} {
## ad_ip_instance $connect_type axi_mem_interconnect
## }
## set m_interconnect_index $sys_mem_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
## set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells ddr_axi_vip]]
## }
##
## if {$p_sel eq "MEM"} {
## if {$sys_mem_interconnect_index < 0} {
## ad_ip_instance $connect_type axi_mem_interconnect
## }
## set m_interconnect_index $sys_mem_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
## set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl] -filter "USAGE == memory"]
## }
##
## if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
## if {$sys_hp0_interconnect_index < 0} {
## set p_name_int sys_ps7/S_AXI_HP0
## set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
## ad_ip_instance $connect_type axi_hp0_interconnect
## }
## set m_interconnect_index $sys_hp0_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
## }
##
## if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
## if {$sys_hp1_interconnect_index < 0} {
## set p_name_int sys_ps7/S_AXI_HP1
## set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
## ad_ip_instance $connect_type axi_hp1_interconnect
## }
## set m_interconnect_index $sys_hp1_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
## }
##
## if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
## if {$sys_hp2_interconnect_index < 0} {
## set p_name_int sys_ps7/S_AXI_HP2
## set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
## ad_ip_instance $connect_type axi_hp2_interconnect
## }
## set m_interconnect_index $sys_hp2_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
## }
##
## if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
## if {$sys_hp3_interconnect_index < 0} {
## set p_name_int sys_ps7/S_AXI_HP3
## set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
## ad_ip_instance $connect_type axi_hp3_interconnect
## }
## set m_interconnect_index $sys_hp3_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
## }
##
## if {($p_sel eq "HPC0") && ($sys_zynq == 2)} {
## if {$sys_hpc0_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HPC0_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP0 {1} [get_bd_cells sys_ps8]
## set_property CONFIG.PSU__AFI0_COHERENCY {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hpc0_interconnect
## }
## set m_interconnect_index $sys_hpc0_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hpc0_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP0/HPC0_DDR_*]
## }
##
## if {($p_sel eq "HPC1") && ($sys_zynq == 2)} {
## if {$sys_hpc1_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HPC1_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP1 {1} [get_bd_cells sys_ps8]
## set_property CONFIG.PSU__AFI1_COHERENCY {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hpc1_interconnect
## }
## set m_interconnect_index $sys_hpc1_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hpc1_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP1/HPC1_DDR_*]
## }
##
## if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
## if {$sys_hp0_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HP0_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hp0_interconnect
## }
## set m_interconnect_index $sys_hp0_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
## }
##
## if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
## if {$sys_hp1_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HP1_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hp1_interconnect
## }
## set m_interconnect_index $sys_hp1_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
## }
##
## if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
## if {$sys_hp2_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HP2_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hp2_interconnect
## }
## set m_interconnect_index $sys_hp2_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
## }
##
## if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
## if {$sys_hp3_interconnect_index < 0} {
## set p_name_int sys_ps8/S_AXI_HP3_FPD
## set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
## ad_ip_instance $connect_type axi_hp3_interconnect
## }
## set m_interconnect_index $sys_hp3_interconnect_index
## set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
## set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
## }
##
## if {$p_sel eq "NOC"} {
## set m_interconnect_index [get_property CONFIG.NUM_SI [get_bd_cells axi_noc_0]]
## set m_interconnect_cell [get_bd_cells axi_noc_0]
## set m_addr_seg [get_bd_addr_segs axi_noc_0/S[format "%02s" [expr $m_interconnect_index +1]]_AXI/C0_DDR_LOW0]
## set sys_mem_clk_index [expr [get_property CONFIG.NUM_CLKS [get_bd_cells axi_noc_0]]-1]
## }
##
## set i_str "S$m_interconnect_index"
## if {$m_interconnect_index < 10} {
## set i_str "S0$m_interconnect_index"
## }
##
## set m_interconnect_index [expr $m_interconnect_index + 1]
##
## set p_intf_name [lrange [split $p_name_int "/"] end end]
## set p_cell_name [lrange [split $p_name_int "/"] 0 0]
## set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
## $p_intf_clock eq $p_clk_source} {
## set p_intf_clock ""
## }
##
## regsub clk $p_clk resetn p_rst
## if {[get_bd_nets -quiet $p_rst] eq ""} {
## set p_rst sys_cpu_resetn
## }
##
## if {$m_interconnect_index == 0} {
## set_property CONFIG.NUM_MI 1 $m_interconnect_cell
## set_property CONFIG.NUM_SI 1 $m_interconnect_cell
## ad_connect $p_rst $m_interconnect_cell/ARESETN
## ad_connect $p_clk $m_interconnect_cell/ACLK
## ad_connect $m_interconnect_cell/M00_AXI $p_name_int
## if {$use_smartconnect == 0} {
## ad_connect $p_rst $m_interconnect_cell/M00_ARESETN
## ad_connect $p_clk $m_interconnect_cell/M00_ACLK
## }
## if {$p_intf_clock ne ""} {
## ad_connect $p_clk $p_intf_clock
## }
## } else {
##
## set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
## if {$use_smartconnect == 1} {
## set clk_index [lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]]
## if { $clk_index == -1 } {
## incr sys_mem_clk_index
## set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
## ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
## set asocc_clk_pin $m_interconnect_cell/ACLK$sys_mem_clk_index
## } else {
## set asocc_clk_pin [lindex [get_bd_pins $m_interconnect_cell/ACLK*] $clk_index]
## }
## } else {
## ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN
## ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
## }
## ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
## if {$p_intf_clock ne ""} {
## ad_connect $p_clk $p_intf_clock
## }
##
## if {$p_sel eq "NOC"} {
## set_property -dict [list CONFIG.CONNECTIONS {MC_0 { read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}} }] [get_bd_intf_pins /axi_noc_0/${i_str}_AXI]
## # Add the new bus as associated to the clock pin, append new if other exists
## set clk_asoc_port [get_property CONFIG.ASSOCIATED_BUSIF [get_bd_pins $asocc_clk_pin]]
## if {$clk_asoc_port != {}} {
## set clk_asoc_port ${clk_asoc_port}:
## }
## set_property -dict [list CONFIG.ASSOCIATED_BUSIF ${clk_asoc_port}${i_str}_AXI] [get_bd_pins $asocc_clk_pin]
## }
##
## set mem_mapped ""
## if {$p_sel eq "MEM"} {
## # Search a DDR segment that is at least 16MB
## set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -regexp -filter {NAME=~ ".*ddr.*" && RANGE=~".*0{6}$"}]
## }
## if {$p_sel eq "SIM"} {
## set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter {NAME=~ *M_AXI*} -of [get_bd_cells /mng_axi_vip]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
## }
##
## if {$mem_mapped eq ""} {
## assign_bd_address $m_addr_seg
## } else {
## assign_bd_address -offset [get_property OFFSET $mem_mapped] \
## -range [get_property RANGE $mem_mapped] $m_addr_seg
## }
## }
##
## if {($use_smartconnect == 0) && ($m_interconnect_index > 1)} {
## set_property CONFIG.STRATEGY {2} $m_interconnect_cell
## }
##
## if {$p_sel eq "SIM"} {set sys_mem_interconnect_index $m_interconnect_index}
## if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HPC0"} {set sys_hpc0_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HPC1"} {set sys_hpc1_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
## if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
##
## }
## proc ad_hpmx_interconnect {p_sel p_address p_name {p_intf_name {}}} {
##
## global sys_zynq
## global use_smartconnect
##
## set interconnect_name [format "axi_%s_interconnect" [string tolower $p_sel]]
##
## if {[catch {
## set interconnect_index [get_property CONFIG.NUM_MI [get_bd_cells $interconnect_name]]
## } err]} {
## set interconnect_index 0
## }
## set i_str [format "M%02d" $interconnect_index]
##
## if {$i_str eq "M00"} {
##
## if {$use_smartconnect == 1} {
## ad_ip_instance smartconnect $interconnect_name [ list \
## NUM_MI 1 \
## NUM_SI 1 \
## ]
## ad_connect sys_cpu_clk $interconnect_name/aclk
## ad_connect sys_cpu_resetn $interconnect_name/aresetn
## } else {
## ad_ip_instance axi_interconnect $interconnect_name
## ad_connect sys_cpu_clk $interconnect_name/ACLK
## ad_connect sys_cpu_clk $interconnect_name/S00_ACLK
## ad_connect sys_cpu_resetn $interconnect_name/ARESETN
## ad_connect sys_cpu_resetn $interconnect_name/S00_ARESETN
## }
##
## if {$sys_zynq == 3} {
## ad_connect sys_cpu_clk sys_cips/m_axi_fpd_aclk
## ad_connect $interconnect_name/S00_AXI sys_cips/M_AXI_FPD
## } elseif {($p_sel eq "HPM0_FPD") && ($sys_zynq == 2)} {
## ad_connect sys_cpu_clk sys_ps8/maxihpm0_fpd_aclk
## ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM0_FPD
## } elseif {($p_sel eq "HPM1_FPD") && ($sys_zynq == 2)} {
## ad_connect sys_cpu_clk sys_ps8/maxihpm1_fpd_aclk
## ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM1_FPD
## } elseif {($p_sel eq "HPM0_LPD") && ($sys_zynq == 2)} {
## ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
## ad_connect $interconnect_name/S00_AXI sys_ps8/M_AXI_HPM0_LPD
## } elseif {($p_sel eq "GP0") && ($sys_zynq == 1)} {
## ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
## ad_connect $interconnect_name/S00_AXI sys_ps7/M_AXI_GP0
## } elseif {($p_sel eq "GP1") && ($sys_zynq == 1)} {
## ad_connect sys_cpu_clk sys_ps7/M_AXI_GP1_ACLK
## ad_connect $interconnect_name/S00_AXI sys_ps7/M_AXI_GP1
## } elseif {$sys_zynq == 0} {
## ad_connect $interconnect_name/S00_AXI sys_mb/M_AXI_DP
## } elseif {$sys_zynq == -1} {
## ad_connect $interconnect_name/S00_AXI mng_axi_vip/M_AXI
## }
## }
##
## if {$sys_zynq == 3} {
## set sys_addr_cntrl_space [get_bd_addr_spaces /sys_cips/M_AXI_FPD]
## }
## if {$sys_zynq == 2} {
## set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
## }
## if {$sys_zynq == 1} {
## set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
## }
## if {$sys_zynq == 0} {
## set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
## }
## if {$sys_zynq == -1} {
## set sys_addr_cntrl_space [get_bd_addr_spaces mng_axi_vip/Master_AXI]
## }
##
## set interconnect_index [expr $interconnect_index + 1]
##
## set p_cell [get_bd_cells $p_name]
## set p_intf [get_bd_intf_pins -filter \
## "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0 && NAME =~ *$p_intf_name*"\
## -of_objects $p_cell]
##
## set p_hier_cell $p_cell
## set p_hier_intf $p_intf
##
## while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
## set p_hier_intf [find_bd_objs -boundary_type lower \
## -relation connected_to $p_hier_intf]
## if {$p_hier_intf != {}} {
## set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
## } else {
## set p_hier_cell {}
## }
## }
##
## set p_intf_clock ""
## set p_intf_reset ""
##
## if {$p_intf_name eq ""} {
## set p_intf_name_bu ""
## } else {
## set p_intf_name_bu _${p_intf_name}
## }
##
## if {$p_hier_cell != {}} {
## set p_intf_name [lrange [split $p_hier_intf "/"] end end]
##
## set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
## (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
## -quiet -of_objects $p_hier_cell]
## set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
## (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
## CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
## -quiet -of_objects $p_hier_cell]
##
## if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
## set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
## if {$p_intf_reset ne ""} {
## set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
## }
## }
##
## # Trace back up
## set p_hier_cell2 $p_hier_cell
##
## while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
## puts $p_intf_clock
## puts $p_hier_cell2
## set p_intf_clock [find_bd_objs -boundary_type upper \
## -relation connected_to $p_intf_clock]
## if {$p_intf_clock != {}} {
## set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
## set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
## }
## }
##
## set p_hier_cell2 $p_hier_cell
##
## while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
## set p_intf_reset [find_bd_objs -boundary_type upper \
## -relation connected_to $p_intf_reset]
## if {$p_intf_reset != {}} {
## set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
## set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
## }
## }
## }
##
##
## if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
## set p_intf_clock ""
## }
## if {$p_intf_reset ne ""} {
## if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
## set p_intf_reset ""
## }
## }
##
## set_property CONFIG.NUM_MI $interconnect_index [get_bd_cells $interconnect_name]
##
## if {$use_smartconnect == 0} {
## ad_connect sys_cpu_clk $interconnect_name/${i_str}_ACLK
## ad_connect sys_cpu_resetn $interconnect_name/${i_str}_ARESETN
## }
## if {$p_intf_clock ne ""} {
## ad_connect sys_cpu_clk ${p_intf_clock}
## }
## if {$p_intf_reset ne ""} {
## ad_connect sys_cpu_resetn ${p_intf_reset}
## }
## ad_connect $interconnect_name/${i_str}_AXI ${p_intf}
##
## set p_seg [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter "NAME=~ *${p_intf_name}*" -of $p_hier_cell]]]
## set p_index 0
## foreach p_seg_name $p_seg {
## if {$p_index == 0} {
## set p_seg_range [get_property range $p_seg_name]
## if {$p_seg_range < 0x1000} {
## set p_seg_range 0x1000
## }
## if {$sys_zynq == 3} {
## if {($p_address >= 0x44000000) && ($p_address <= 0x4fffffff)} {
## # place axi peripherics in A400_0000-AFFF_FFFF range
## set p_address [expr ($p_address + 0x60000000)]
## } elseif {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
## # place axi peripherics in B000_0000-BFFF_FFFF range
## set p_address [expr ($p_address + 0x40000000)]
## } else {
## error "ERROR: ad_cpu_interconnect : Cannot map ($p_address) to aperture, \
## Addess out of range 0x4400_0000 - 0X4FFF_FFFF; 0x7000_0000 - 0X7FFF_FFFF !"
## }
## }
## if {$sys_zynq == 2} {
## if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
## set p_address [expr ($p_address + 0x40000000)]
## }
## if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
## set p_address [expr ($p_address + 0x20000000)]
## }
## }
## puts "create_bd_addr_seg -range $p_seg_range -offset $p_address $sys_addr_cntrl_space $p_seg_name SEG_data_${p_name}${p_intf_name_bu}"
## create_bd_addr_seg -range $p_seg_range \
## -offset $p_address $sys_addr_cntrl_space \
## $p_seg_name "SEG_data_${p_name}${p_intf_name_bu}"
## } else {
## assign_bd_address $p_seg_name
## }
## incr p_index
## }
## }
## proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
##
## global sys_zynq
##
## if {$sys_zynq == -1} {
## ad_hpmx_interconnect "AXI" $p_address $p_name $p_intf_name
## } elseif {$sys_zynq == 0} {
## ad_hpmx_interconnect "DP" $p_address $p_name $p_intf_name
## } elseif {$sys_zynq == 1} {
## ad_hpmx_interconnect "GP0" $p_address $p_name $p_intf_name
## } elseif {$sys_zynq == 2} {
## ad_hpmx_interconnect "HPM0_LPD" $p_address $p_name $p_intf_name
## } elseif {$sys_zynq == 3} {
## ad_hpmx_interconnect "FPD" $p_address $p_name $p_intf_name
## }
## }
## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
##
## global sys_zynq
##
## if {$sys_zynq <= 0} {set p_index_int $p_mb_index}
## if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
##
## set p_index [regsub -all {[^0-9]} $p_index_int ""]
## set m_index [expr ($p_index - 8)]
##
## if {$sys_zynq == 3} {
## if {$p_index < 0 || $p_index > 15} {
## error "ERROR: ad_cpu_interrupt : Interrupt index ($p_index) out of range 0-15 "
## }
## ad_connect $p_name sys_cips/pl_ps_irq$p_index
## }
##
## if {($sys_zynq == 2) && ($p_index <= 7)} {
## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
## set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
##
## puts "disconnect_bd_net $p_net $p_pin"
## disconnect_bd_net $p_net $p_pin
## ad_connect sys_concat_intc_0/In$p_index $p_name
## }
##
## if {($sys_zynq == 2) && ($p_index >= 8)} {
## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
## set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
##
## puts "disconnect_bd_net $p_net $p_pin"
## disconnect_bd_net $p_net $p_pin
## ad_connect sys_concat_intc_1/In$m_index $p_name
## }
##
## if {$sys_zynq <= 1} {
##
## set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
## set p_pin [get_bd_pins sys_concat_intc/In$p_index]
##
## puts "disconnect_bd_net $p_net $p_pin"
## disconnect_bd_net $p_net $p_pin
## ad_connect sys_concat_intc/In$p_index $p_name
## }
## }
# set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
# set BOARD_NAME zed
# adi_project fmcomms2_${BOARD_NAME}
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts'.
CRITICAL WARNING: vivado version mismatch; expected 2025.1, got 2021.2.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/sanjai/Desktop/zed/hdl/hdl/library'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/sanjai/Documents/Vivado_files/Vivadooo/vitis/Vivado/2021.2/data/ip'.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Synth 8-2490} -new_severity WARNING
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
Wrote : </home/sanjai/Desktop/zed/hdl/hdl/projects/fmcomms2/zed/fmcomms2_zed.srcs/sources_1/bd/system/system.bd>
INFO: [BD 41-2613] The output directory /home/sanjai/Desktop/zed/hdl/hdl/projects/fmcomms2/zed/fmcomms2_zed.gen/sources_1/bd/system for system cannot be found.
## source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
### set CACHE_COHERENCY false
### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
### create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
### create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc
### create_bd_port -dir O spi0_csn_2_o
### create_bd_port -dir O spi0_csn_1_o
### create_bd_port -dir O spi0_csn_0_o
### create_bd_port -dir I spi0_csn_i
### create_bd_port -dir I spi0_clk_i
### create_bd_port -dir O spi0_clk_o
### create_bd_port -dir I spi0_sdo_i
### create_bd_port -dir O spi0_sdo_o
### create_bd_port -dir I spi0_sdi_i
### create_bd_port -dir O spi1_csn_2_o
### create_bd_port -dir O spi1_csn_1_o
### create_bd_port -dir O spi1_csn_0_o
### create_bd_port -dir I spi1_csn_i
### create_bd_port -dir I spi1_clk_i
### create_bd_port -dir O spi1_clk_o
### create_bd_port -dir I spi1_sdo_i
### create_bd_port -dir O spi1_sdo_o
### create_bd_port -dir I spi1_sdi_i
### create_bd_port -dir I -from 63 -to 0 gpio_i
### create_bd_port -dir O -from 63 -to 0 gpio_o
### create_bd_port -dir O -from 63 -to 0 gpio_t
### create_bd_port -dir O hdmi_out_clk
### create_bd_port -dir O hdmi_hsync
### create_bd_port -dir O hdmi_vsync
### create_bd_port -dir O hdmi_data_e
### create_bd_port -dir O -from 15 -to 0 hdmi_data
### create_bd_port -dir O -type clk i2s_mclk
### create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
### create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i
### create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o
### create_bd_port -dir O iic_mux_scl_t
### create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i
### create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o
### create_bd_port -dir O iic_mux_sda_t
### create_bd_port -dir I otg_vbusoc
### create_bd_port -dir O spdif
### ad_ip_instance processing_system7 sys_ps7
### ad_ip_parameter sys_ps7 CONFIG.PCW_IMPORT_BOARD_PRESET ZedBoard
INFO: [PS7-1] Applying Board Preset ZedBoard...
### ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP0 1
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA0 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA1 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA2 1
### ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values.
### ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO
### ad_ip_instance axi_iic axi_iic_main
### ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
### ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE Custom
### ad_ip_instance util_i2c_mixer sys_i2c_mixer
### ad_ip_instance ilconcat sys_concat_intc
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell sys_concat_intc
ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name sys_concat_intc .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}"
(procedure "ad_ip_instance" line 7)
invoked from within
"ad_ip_instance ilconcat sys_concat_intc"
(file "/home/sanjai/Desktop/zed/hdl/hdl/projects/common/zed/zed_system_bd.tcl" line 96)
while executing
"source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl"
(file "system_bd.tcl" line 6)
while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 136)
invoked from within
"adi_project_create $project_name $mode $parameter_list $device $board"
(procedure "adi_project" line 80)
invoked from within
"adi_project fmcomms2_${BOARD_NAME}"
(file "system_project.tcl" line 12)
INFO: [Common 17-206] Exiting Vivado at Wed Feb 4 13:55:35 2026...
Regards,
PADT
Edit Notes
Error Log Addition[edited by: ParasADT at 8:35 AM (GMT -5) on 4 Feb 2026]
