AD9361 DATA_CLK cannot reach 25 MHz with 50 MHz reference clock

I’m working with the AD9361 in a 2Rx/2Tx configuration with a 50 MHz reference clock. My goal is to achieve a DATA_CLK of 25 MHz (or at least 50 MHz), but despite adjusting the RX/TX path clocks and FIR settings, I am only seeing 30 MHz or 60 MHz on the data interface.

Here are the details of my configuration:

Reference Clock: 50 MHz

uint32_t rx_path_clock_frequencies[6] = {800000000, 50000000, 25000000, 25000000, 25000000, 25000000};

uint32_t tx_path_clock_frequencies[6] = {800000000, 50000000, 25000000, 25000000, 25000000, 25000000};

Observations:

• After enabling the RX/TX FIR, DATA_CLK remains at 30 MHz.
• Increasing BBPLL to higher frequencies (e.g., 800 MHz) gives ~30 MHz, but the datasheet mentions BBPLL minimum is 715 MHz.
• Using smaller BBPLL (715 MHz) doesn’t give the desired DATA_CLK of 25 MHz.
• I have tried various rx_path_clock_frequencies and tx_path_clock_frequencies combinations, but the DATA_CLK is not reaching 25 MHz.

Additional Notes:

• AD9361 reports PLLs and LO locked.

Question:

• Is there a valid combination of reference clock, path clocks, and FIR settings that can produce 25 MHz DATA_CLK with 50 MHz reference clock?
• Are there internal constraints (BBPLL or dividers) that prevent reaching 25 MHz exactly?

Any guidance or example configuration to achieve this DATA_CLK would be greatly appreciated.

Thank you!