I’m running an AD9361 on a ZynqMP-based design in 2Rx-2Tx (MIMO), LVDS/DDR mode and I’m hitting the following issue: I ran the 1rx1tx mode. It didn't give any errors. When I switched to 2rx2tx mode, I set it to MIMO 1. And then these errors started occurring. RX tuning succeeds , but TX tuning fails with: ad9361_dig_tune_delay: Tuning TX FAILED! 2Rx-2Tx requirement & DTSI notes I specifically need true 2Rx-2Tx operation (both RX channels and both TX channels active). I reviewed multiple example DTSIs online; for 2×2 MIMO the only additional property I consistently saw was: adi,2rx-2tx-mode-enable; In my DTSI, auto-tune is enabled : adi,digital-interface-tune-skip-mode = <0>; (i.e., I’m using the driver’s built-in tuning flow; no manual delay overrides in this mode.) I’m not using the 1×1-only properties (e.g., adi,1rx-1tx-mode-use-rx-num , adi,1rx-1tx-mode-use-tx-num ).

AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS)

ErsinCengiz

on Nov 14, 2025

Category: Software

Product Number: AD9361

Software Version: petalinux & vivado 2021.2

I’m running an AD9361 on a ZynqMP-based design in 2Rx-2Tx (MIMO), LVDS/DDR mode and I’m hitting the following issue:

I ran the 1rx1tx mode. It didn't give any errors. When I switched to 2rx2tx mode, I set it to MIMO 1. And then these errors started occurring.

RX tuning succeeds, but TX tuning fails with:

ad9361_dig_tune_delay: Tuning TX FAILED!

2Rx-2Tx requirement & DTSI notes

I specifically need true 2Rx-2Tx operation (both RX channels and both TX channels active).
I reviewed multiple example DTSIs online; for 2×2 MIMO the only additional property I consistently saw was:

adi,2rx-2tx-mode-enable;
In my DTSI, auto-tune is enabled:

adi,digital-interface-tune-skip-mode = <0>;

(i.e., I’m using the driver’s built-in tuning flow; no manual delay overrides in this mode.)
I’m not using the 1×1-only properties (e.g., adi,1rx-1tx-mode-use-rx-num, adi,1rx-1tx-mode-use-tx-num).

Edit Notes

I ran the 1rx1tx mode. It didn't give any errors. When I switched to 2rx2tx mode, I set it to MIMO 1. And then these errors started occurring.
[edited by: ErsinCengiz at 7:49 AM (GMT -5) on 14 Nov 2025]

petalinux & vivado 2021.2 software ad9361 Tx tune error Wideband Transceiver IC 2rx-2tx RF Integrated Transceivers Show More

SJagini

on Nov 14, 2025 7:34 AM
0
Hi ErsinCengiz

Pls try with following

Option 1: Manual Delay Override

If auto-tune fails, set:

///////////////////////////////////////

adi,digital-interface-tune-skip-mode = <2>;

/////////////////////////////////////////

and provide manual delay values:

//////////////////////////////////////////

adi,rx-data-delay = <3>;

adi,tx-data-delay = <4>;

adi,rx-data-clock-delay = <0>;

//////////////////////////////////////////

(Values depend on your board; start with defaults from ADI reference designs.)

Option 2: Verify HDL

Ensure you are using the latest ADI HDL for ZynqMP with 2×2 MIMO enabled.

Option 3: Reduce Lane Rate

Lower the sample rate temporarily to relax timing and confirm if tuning passes.

These might help.

Regards,

SJ
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ErsinCengiz
on Nov 17, 2025 5:03 AM in reply to SJagini
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Thank you very much for replying so quickly. This is an urgent issue for me that needs to be solved.

I set adi,digital-interface-tune-skip-mode = <0>; because I saw it like that in the example DTSI files.
When I set this mode to 2, tuning is not performed, so I don’t get an error.
However, in all the example files it is recommended to keep this mode at 0.
With 2 it simply skips tuning, so that error is bypassed.

I’ll show you two different scenarios as examples.

Option 1

Scenario 1

When the example settings in pl-custom.dtsi are like this:

adi,digital-interface-tune-skip-mode = <2>; adi,pp-tx-swap-enable; adi,pp-rx-swap-enable; adi,rx-frame-pulse-mode-enable; adi,lvds-mode-enable; adi,lvds-bias-mV = <150>; adi,lvds-rx-onchip-termination-enable; adi,rx-data-delay = <4>; adi,tx-data-delay = <3>; adi,tx-fb-clock-delay = <7>;

the Linux output I observe is:

[ 10.121956] ad9361 spi2.0: ad9361_probe : enter (ad9361) [ 10.128140] ad9361 spi2.0: No GPIOs defined for ext band ctrl [ 10.261841] ad9361 spi2.0: ad9361_probe : AD936x Rev 0 successfully initialized [ 10.293187] cf_axi_adc 80000000.cf-ad9361-lpc: ADI AIM (10.03.0) at 0x80000000 mapped to 0x00000000063b3424 probed ADC AD9361 as MASTER [ 10.317940] cf_axi_dds 80004000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x80004000 mapped to 0x000000009381d20f, probed DDS AD9361

Scenario 2

When the example settings in pl-custom.dtsi are like this:

adi,digital-interface-tune-skip-mode = <0>; adi,pp-tx-swap-enable; adi,pp-rx-swap-enable; adi,rx-frame-pulse-mode-enable; adi,lvds-mode-enable; adi,lvds-bias-mV = <150>; adi,lvds-rx-onchip-termination-enable; adi,rx-data-delay = <4>; adi,tx-fb-clock-delay = <7>;

the Linux output I observe is:

[ 10.728023] ad9361 spi2.0: ad9361_probe : enter (ad9361) [ 10.734192] ad9361 spi2.0: No GPIOs defined for ext band ctrl [ 10.856223] ad9361 spi2.0: ad9361_probe : AD936x Rev 0 successfully initialized [ 11.289816] SAMPL CLK: 61440000 tuning: RX [ 11.293928] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: [ 11.298419] 0:# o o O o o # # # # # # # # # # [ 11.302905] 1:# # # # # # # # # # # # # # # # [ 11.307392] co (5), c1 (0) [ 11.716950] SAMPL CLK: 61440000 tuning: TX [ 11.721053] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f: [ 11.725538] 0:# # # # # # # # # # # # # # # # [ 11.730025] 1:# # # # # # # # # # # # # # # # [ 11.734513] co (0), c1 (0) [ 11.737222] ad9361 spi2.0: ad9361_dig_tune_delay: Tuning TX FAILED! [ 11.744133] cf_axi_adc: probe of 80000000.cf-ad9361-lpc failed with error -5 [ 11.764322] cf_axi_dds 80004000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x80

Option 2

Tests were conducted with MIMO 1 active.

Option 3

The settings for this section are as follows.

adi,rx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;
adi,tx-path-clock-frequencies = <983040000 245760000 122880000 61440000 30720000 30720000>;

Even though I adjusted it this way, the result didn't change. It's still giving the same error.

As additional information, I was able to run rx1tx1. When I switch to 2rx2tx, I encounter this issue. HDL version 2022.

The output on rx1tx1 is working successfully in this manner. When I try to do 2rx2tx, it doesn't work.

[ 11.072859] ad9361 spi2.0: ad9361_probe : enter (ad9361)
[ 11.229324] ad9361 spi2.0: ad9361_probe : AD936x Rev 0 successfully initialized
[ 11.664627] SAMPL CLK: 61440000 tuning: RX
[ 11.668737] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 11.673227] 0:# o o o o o o O o o o o o o # #
[ 11.677714] 1:# # # # # # # # # # # # # # # #
[ 11.682201] co (13), c1 (0)
[ 12.091584] SAMPL CLK: 61440000 tuning: TX
[ 12.095681] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 12.100166] 0:# # # # # # # # # # # # # # # #
[ 12.104652] 1:# # o o o o o o O o o o o o o #
[ 12.109140] co (0), c1 (13)
[ 12.115715] cf_axi_adc 80000000.cf-ad9361-lpc: ADI AIM (10.03.0) at 0x80000000 mapped to 0x000000005d03865b probed ADC AD9364 as MASTER
[ 12.141118] cf_axi_dds 80004000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x80004000 mapped to 0x00000000eef1fd79, probed DDS AD9361

I don't know what else to do. I lowered the sample rate from 61440000 to 30720000, but it still gave the same error. All of the above tests were tried at a sample rate of 30720000.

I need your help with this. It's an urgent matter for me. Thank you for your help.
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SJagini

on Nov 17, 2025 5:37 AM in reply to ErsinCengiz
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HI ErsinCengiz

Common causes for the above problem.

Clocking mismatch:

Your sample clock (61.44 MHz or 30.72 MHz) must match HDL design constraints.

Check adi,rx-path-clock-frequencies and adi,tx-path-clock-frequencies in DTSI.

LVDS delays:

adi,rx-data-delay, adi,tx-data-delay, and adi,tx-fb-clock-delay may need adjustment.

Defaults often assume FMC reference designs, not custom boards.

Board skew:

PCB trace length differences can break auto-tuning.

Pls try following by keeping digital interface tuning mode = 0

Adjust delays manually:

adi,rx-data-delay = <4>;

adi,tx-data-delay = <3>;

adi,tx-fb-clock-delay = <7>;

Try sweeping these values (e.g., 0–15) to find a stable combination.

Ensure LVDS bias and termination:

adi,lvds-mode-enable;

adi,lvds-bias-mV = <150>;

adi,lvds-rx-onchip-termination-enable;

Lower sample rate temporarily (e.g., 15.36 MHz) to widen timing margin.

Watch kernel log during tuning:

RX tuning matrix should show at least one valid window (O).

TX tuning matrix failing means feedback clock alignment is off.

If no valid window:

Increment tx-fb-clock-delay and retry.

If still failing, try rx-data-delay and tx-data-delay.

if you are bypassing digital interface tune, there is risk of Data corruption at high rates.

Regards,

SJ
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ErsinCengiz
on Nov 21, 2025 12:20 AM in reply to SJagini
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I found the root cause of the problem. It was due to an incorrect pin connection on the HDL side of the Tx path. Thank you for your help.
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SJagini

on Nov 28, 2025 3:55 AM in reply to ErsinCengiz
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HI ErsinCengiz

Thanks for the update. Good to hear your problem is solved.

we will close the thread.

Regards.

SJ
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AD9361 – “ad9361_dig_tune_delay: Tuning TX FAILED!” (ZynqMP / Vivado 2021.2, 2Rx-2Tx LVDS)

2Rx-2Tx requirement & DTSI notes

Edit Notes

Scenario 1

Scenario 2